[SI-LIST] Re: HCSL Input Terminations
- From: "Mustafa Yousuf" <yousufs432@xxxxxxxxx>
- To: <dudi@xxxxxxxxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Mon, 29 Jul 2013 16:38:17 -0700
Hi Dudi,
Termination to the buffer varies according to what is driving it and the
output signal level of the driver. This should be compatible with the input
requirements of the HCSL input buffer for level shifting and common mode.
Best thing is to consult the app notes from IDT of the CLK buffer (IDT
device) you are using and what they recommend for each case.
Regards,
Mustafa Yousuf
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Dudi Tash
Sent: Monday, July 29, 2013 11:50 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] HCSL Input Terminations
Hi All,
For a new design, I'm using a Clock Buffer for the PCIe REFCLK.
The interface is called HCSL, but I'm trying to figure out which
terminations should be added externally to the receiver (INPUT) of the clock
buffer.
I'm using the IDT 9DBV0841 as the clock buffer and I'm familiar with the
required output termination, (33Ohm in series and 50 Ohm to GND), but I
couldn't find anything for the input terminations.
Please advise.
Thanks
Best Regards,
Dgtronix Ltd. I Founder & CEO I Dudi Tash
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