[SI-LIST] Re: HBA PCIe gen2 test w/o using CBB
- From: Nathan JP <jpnathan@xxxxxxxxxxx>
- To: <sherman.chen@xxxxxxx>, "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Wed, 2 Jul 2014 00:19:16 +0530
Hi Sherman,
The below given set-up should be ok for measuring the gen-2 signal quality
transmitted from PCIe card.
Note:
Assuming that the Compliance test pattern is forced from the PCIe device in HBA
card.
Also, if the HBA card uses a local Ref-Clk, it's Clk Jitter can be measured
separately. Else, a low jitter external Ref-Clk need to be fed.
CEM 2.0 Tx spec (for Add-in Card) can be used for measuring gen-2 express card
signals quality (either in Scope SW or with Sigtest tool).
Regards,
Nathan JP
________________________________
From: Chen, Sherman<mailto:sherman.chen@xxxxxxx>
Sent: â01-â07-â2014 22:07
To: si-list@xxxxxxxxxxxxx<mailto:si-list@xxxxxxxxxxxxx>
Subject: [SI-LIST] HBA PCIe gen2 test w/o using CBB
Dear PCIEers,
I believe in this list there are quite a lot of experts who have deep
understanding on PCIe spec. as well as test practice. So here is my question:
We are thinking to evaluate the gen2 signal quality as well as the REF_CLK of
one HBA card. For some reason we don't plan to use CBB unless we have to. Thus
the test procedure has to be altered on some aspects. Mainly they are:
1. the test point is at the PCIe connector rather than SMP or REF_CLK
connector.
2. the connection means is changed from SMP2SMA adaptor + SMA cable to
diff probe.
The captured waveform will be fed into Sigtest/PCIe clock jitter tool to
generate the test result.
Will above method still give a result very close to the result obtained by
using CBB? Personally I don't see big difference will be produced here...
And, if we drops Sigtest/jitter tool, and use scope to measure the
EH/EW/Jitter. What criteria shall we follow - CEM3.0 TX/RX spec.?
Best regards,
Sherman Chen
Signal Integrity
EMC Global Hardware Engineering
Tel: +86 21 60951100ext3329
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