[SI-LIST] Re: Guard Traces

  • From: Eric Steimle <eric.steimle@xxxxxxxxxx>
  • To: "colin@xxxxxxxxxxx" <colin@xxxxxxxxxxx>, "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
  • Date: Mon, 12 Mar 2012 17:37:19 +0000

All this talk about low cost consumer boards brings back memories, before I 
switched to networking I did a lot of consumer product boards that were limited 
to two layers.   We even did DDR2 and USB HS on 2 layer boards, although I 
wouldn't advise anyone to try it ;)  Our tool vendors just threw up their hands 
and said good luck when we asked if they could simulate the return currents 
(except maybe some expensive 3D solvers and if you don't have money for 4 layer 
boards... who's going to buy you that).  

Eventually we found, at least at our volumes (1M+/year) that four layer boards 
really weren't all that much more expensive than a two layer.   Maybe $0.25 - 
$0.50 more depending on area, and most of our customers with better engineering 
departments switched over as speeds went up.  Granted that translates into 
$250k - $500k in revenue, but you also have to consider how much more 
engineering dollars have to be spent to make those two layer boards work, how 
much more trouble we had getting through FCC, and how much later the products 
showed up to market because of all that extra effort.

But all my talking may still not void that $250k savings that management is 
drooling over.  In your case you are probably doing the best you can, you could 
also try GND flooding the area on layer 2 underneath the SPI traces from chip 
to chip.   I'll assume your boards are around 62 mil so that's a big distance 
but better than nothing.  
 
I think your assumption that there will be near zero current flow is correct at 
DC but at AC you have to consider the current that the driver will need to 
drive the transmission line which will be considerably more.  Probably whatever 
the SPI voltage / (transmission line impedance plus the drivers output 
impedance).  It's a complex problem since it'll be hard for you to characterize 
the impedance of that transmission line.  Basically though the moment that 
driver activates its output transistors it's driving current to try to overcome 
the capacitance, inductance and resistances that make up the line impedance.   
That current will flow through whatever is the path of least impedance, which 
in your case sounds like your "return" traces, but may also include any of the 
cross hatching, or anything else convenient to it as it tries to make its way 
back to the chip.

If you take a look at some of the texts or sites out there that talk about 
using an RLC model for a transmission line, and how return current flows it 
might help in understanding how it will flow in your system and why.  Oh and be 
careful with those guard traces, as someone pointed out earlier today every 
little deviation is an impedance discontinuity.   Such as the guard trace just 
doesn't fit so you leave it out in a section, or the spacing varies.


Good luck!
-Eric   

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On 
Behalf Of Colin D Bennett
Sent: Monday, March 12, 2012 12:58 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Guard Traces

On Sun, 11 Mar 2012 20:40:54 -0700
Aaditya Kandibanda <aaditya.kandibanda@xxxxxxxxx> wrote:

> Hello Mr Ritchey,
> If I have a trace which is stitched to ground at both ends along side 
> of a another trace, will there be any current loop formed which 
> creates a EM radiation between the two traces? what path will return 
> current take?

I have the same question.  For instance, one design uses a two-layer PCB with 
an 18 MHz SPI bus between two ICs... there is no ground/power plane.  I tried 
to heavily grid the power and ground on the board.  A multi-layer board would 
be great, but many consumer products and high-volume low-cost sensor network 
devices can't bear the extra cost.

In the first prototype of this board (yet to be tested), I put ground traces on 
both sides of the SPI signals because I was led to understand this will provide 
the lowest-impedance path for return current and thus the smallest possible 
current loop, since there is no real ground plane.

If seems at first that an SPI bus (not terminated at either end, so near zero 
current into receiver) would exhibit more capacitive coupling effects than 
inductive since the current flow is minimal, but voltage swings on the signal 
lines are significant.
(Capacitive coupling being generally based on dv/dt and inductive being based 
on di/dt?)

Regards,
Colin
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