[SI-LIST] Re: Guard Traces

  • From: Colin D Bennett <colin@xxxxxxxxxxx>
  • To: si-list@xxxxxxxxxxxxx
  • Date: Mon, 12 Mar 2012 09:58:12 -0700

On Sun, 11 Mar 2012 20:40:54 -0700
Aaditya Kandibanda <aaditya.kandibanda@xxxxxxxxx> wrote:

> Hello Mr Ritchey,
> If I have a trace which is stitched to ground at both ends along
> side of a another trace, will there be any current loop formed
> which creates a EM radiation between the two traces? what path
> will return current take?

I have the same question.  For instance, one design uses a two-layer
PCB with an 18 MHz SPI bus between two ICs... there is no
ground/power plane.  I tried to heavily grid the power and ground
on the board.  A multi-layer board would be great, but many
consumer products and high-volume low-cost sensor network devices
can't bear the extra cost.

In the first prototype of this board (yet to be tested),
I put ground traces on both sides of the SPI signals because I was
led to understand this will provide the lowest-impedance path for
return current and thus the smallest possible current loop, since
there is no real ground plane.

If seems at first that an SPI bus (not terminated at either end, so
near zero current into receiver) would exhibit more capacitive
coupling effects than inductive since the current flow is minimal,
but voltage swings on the signal lines are significant.
(Capacitive coupling being generally based on dv/dt and inductive
being based on di/dt?)

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