Chris, In some previous platforms, we chose to generate VTT and VDDQ separately = but with tight tolerances on both of 1-2%. In most of our reference = boards and in customer platforms, VTT is always generated from a divider = off of VDDQ. =20 The intent of this is to ensure DC tracking only, not rejection of = common mode noise. There is no need to make the VTT track AC noise in = any case, our only goal is to make it act like a voltage source across = the frequency range we need while coupling the minimum amount of noise = between signals. =20 It might be possible to get some common-mode reduction by generating = VREF at the driver and piping it to the receiver as a signal (as in = AGP4x) but the existing DIMM layouts don't support this, and I doubt the = benefits would be worth the extra pin(s) and the routing hassle. regards, Jeremy -----Original Message----- From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Chris Cheng Sent: Thursday, December 12, 2002 4:29 PM Cc: si-list@xxxxxxxxxxxxx Subject: [SI-LIST] Re: Ground, the preferred reference plane Jeremy, You know what, I stand corrected. You own company's reference schematics shows the VDDQ and VTT are generated from two seperated resistor = dividers and going to two seperate feedbacks. Hard for me to imagine they even = track each other. Chris -----Original Message----- From: Chris Cheng [mailto:chris.cheng@xxxxxxxxxxxx] Sent: Thursday, December 12, 2002 4:09 PM Cc: si-list@xxxxxxxxxxxxx Subject: [SI-LIST] Re: Ground, the preferred reference plane No there is no confusion. Even though the VTT is generated by the using VDDQ/2 as reference to the voltage regulator any high speed changes on = VTT will not be propagate back to VDDQ and vice versa. They are just DC = tracking each other but AC isolated. -----Original Message----- From: Jeremy Plunkett [mailto:jeremy@xxxxxxxxxxxxxxx] Sent: Thursday, December 12, 2002 3:47 PM To: chris.cheng@xxxxxxxxxxxx Cc: si-list@xxxxxxxxxxxxx Subject: RE: [SI-LIST] Re: Ground, the preferred reference plane Hi Chris, I think you are mixing up Vref and Vtt...Vref is the threshold reference provided to each DDR DIMM and controller ASIC, the only current drawn on = it is leakage from the input comparators. Therefore Vref is typically generated by a voltage divider off of VDDQ as close as possible to the = chip it is supplying, and the number of resistors required is quite = reasonable. Vtt on the other hand is the termination supply for all the DDR signals = and must source and sink substantial amounts of current. This requires a = DC/DC converter, but still the VTT should be set up to track the VDDQ voltage = to a tight tolerance by using a voltage divider from VDDQ(suitably filtered) = as the reference voltage for the regulator. regards, Jeremy ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List archives are viewable at: =20 //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages=20 Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu =20 ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu