[SI-LIST] Re: Ground, the preferred reference plane

  • From: Mike Brown <bmgman@xxxxxxxxxx>
  • To: chris.cheng@xxxxxxxxxxxx
  • Date: Wed, 11 Dec 2002 20:05:29 -0600

Chris,

Beg to differ on the ECL reference.  Conventional ECL operates between 
Ground (+v) and -Vee.  The most positive voltage is the reference to 
which the Vbb bias voltage is referred.  The current source in the 
emitter circuit of the diff pair allow Vee to move around quite a bit 
without seriously changing the output voltage levels.  Those levels are 
established by a current source driving a resistor returned to +v.

*Most* other technologies derive their switching threshold reference 
voltage with respect to the negative rail.  Also "ground", or common, in 
those technologies.  TTL, RTL and DTL (Yes, I'm old enough to have used 
them) switching reference voltage is based on junction drops above the 
negative rail.  Those thresholds is relatively independent of Vcc. Thus 
the negative rail is the reference plane. CMOS is a bit different - it 
is based on FET threshold voltages, referenced to both rails.  Its 
switching threshold moves if the Vdd-Vss difference changes.

The choice of "preferred" reference plane is dictated by which voltage 
the technology derives the receiver switching threshold from.  This 
permits the use of split power planes (either +v or -v) in systems which 
are too large to run from a single power source.  It gets nightmarish if 
you don't do this.

Imagine a multi-supply ECL system in which the negative plane was 
common.  The signals interfacing between power zones have a built-in 
differential mode offset equal to the difference in supply voltages.  Or 
a multi-supply TTL system with the + rails commoned.  Same issue.  In 
CMOS, it doesn't make much difference which rail is commoned - there's a 
threshold shift between the different power zones if the supplies are 
different.  And it is a nuisance in large CMOS systems.

Regards

Mike



Chris Cheng wrote:

>Actually there are definite preference on reference plane depending on which
>I/O technology you choose.
>For those old enough to worked on the original ECL (which I am not), the
>prefered reference is the -ve plane not the ground plane. There are a lot of
>open drain I/O's (GTL, ECL to name a few) where the prefer return is the
>voltage the driver's source is tied to. It just happened when Bill Gunning
>started working on GTL he chose to use open drain pull down to ground (to
>save power) and from that point on most of the computers in this world start
>using GTL i/o and thus it makes sense to use ground plane as a reference for
>i/o. Most of the currently so called PECL circuits are shifted up open
>emitters and technically they should be referenced to the power plane rather
>than ground for their return. We are just looking the other way and assuming
>they are perfect differential signals and thus only need to reference
>themselves (+ve vs. -ve), in reality that is not completely ture.
>
>
>
>-----Original Message-----
>From: Loyer, Jeff [mailto:jeff.loyer@xxxxxxxxx]
>Sent: Wednesday, December 11, 2002 12:49 PM
>To: Anand.Kuriakose@xxxxxxx
>Cc: si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Re: Ground, the preferred reference plane
>
>
>
>This has been discussed in great length in this forum.  The archives =
>should have tons of information on it. =20
>
>My short take: the most prevalant cause of problems is changing the =
>reference plane without providing a suitable means for the return =
>current to transition between the planes.  There is much question about =
>what a "suitable means" is - at what frequencies do "stitching caps" =
>become useless, for instance. =20
>
>Since most chips have the signals referenced to ground internally, it is =
>a safer thing to have your signals likewise referenced to ground =
>externally.  This generally applies to cards, also.
>
>In short, it is possible to reference your signals to any plane, but =
>using ground as the reference plane is a safer bet.  An exception might =
>be if a chip specified that their signals were referenced to a power =
>plane, but I haven't seen this.
>
>Jeff Loyer
>
>
>
>-----Original Message-----
>From: Kuriakose, Anand [mailto:Anand.Kuriakose@xxxxxxx]
>Sent: Wednesday, December 11, 2002 12:25 AM
>To: 'si-list@xxxxxxxxxxxxx'
>Subject: [SI-LIST] Ground, the preferred reference plane
>
>
>
>Hi All,
>
>In "High Speed Digital System Design" by Stephen Hall, it is mentioned  =
>that
>the ground-referenced signals have cleaner signal integrity when =
>compared to
>power-referenced signals.=20
>
>Chipset design guides (not all) also recommend to have the high speed
>signals like processor signals routed over ground plane rather than over
>power plane. Also similar statements are made in a few other docs.
>
>I'd like to understand how does it improve the signal integrity of the
>signal when routed over GND plane rather than over power plane. In
>otherwords, what makes GND plane the preffered reference plane?
>
>One other point is that when signals are routed over power planes, the
>return current can get back to where it started without passing through =
>any
>decoupling caps, making the return loop smaller (assuming that signals =
>do
>not cross splits in the plane and no return path discontinuity due to =
>layer
>changes). However, if the same signal is routed over GND plane, the =
>return
>current will have to pass through a decoupling cap to complete the loop.
>Correct me if i am wrong in my above point.=20
>
>Regards,
>Anand.
>
>
>
>
>
>
>
>
>
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