[SI-LIST] Re: Ground plane split widths...
- From: Alan Hilton-Nickel <ahilton@xxxxxxxxxxxxx>
- To: "Johnston, Ross" <RJ182000@xxxxxxxxxxxxxxxxxxxxxxxxx>
- Date: Thu, 08 Aug 2002 07:30:17 -0700
Someone else pointed that out, too. It used to work, but the correct URL for
Doug's website is:
http://emcesd.com/
Lots of good tips there, and if you ever get a chance to attend his seminar, do
it! And no, he does not pay me to say that...:-)
Regards,
Alan
"Johnston, Ross" wrote:
>
> Hi Alan,
>
> Thanks for your comments/guidance on this - perhaps my comments of
> completely isolating were misleading - the IO ground would not be completely
> isolated from the logic ground - the logic ground connects to the chassis
> via the standoffs and screws - the IO ground connects also to the chassis.
> And yes I can now see that I have probably taken the wrong approach on the
> grounding scheme for my board - fortunately I'm working on a new cut at
> present.
>
> Tried your link to the Doug Smith website don't think it has anything to do
> with EMC EMI stuff!!!?
>
> ROSS
>
> -----Original Message-----
> From: Alan Hilton-Nickel [mailto:ahilton@xxxxxxxxxxxxx]
> Sent: 07 August 2002 23:28
> To: Johnston, Ross
> Cc: Si List (E-mail)
> Subject: Re: [SI-LIST] Ground plane split widths...
>
> Ross,
>
> Excuse me, but I am a little confused - how do you plan to "completely
> isolate"
> the ground plane? You still need some DC connection to the power supply
> ground,
> unless you go with an independent IO supply and optoisolators. I suspect you
> are
> looking at some sort of "single point" ground scheme, which connects all the
> grounds at the supply output. This will likely cause problems.
>
> You mention three concerns -
>
> 1. To stop noise coming out from the logic ground onto the I/O signals.
>
> Noise in one area of a ground plane doesn't just "come out" onto your cables
> -
> it has to be coupled in, either by direct conduction through shared return
> paths
> or by radiation. If you lay out the board to minimize the shared
> power/ground
> paths, and your loop inductance is low due to a contiguous ground and power
> plane, there should be no problem.
>
> If you isolate the grounds, you may increase the inductance of the signals
> going
> to the IO circuitry. This will cause them signal to radiate noise onto the
> cables, regardless of how carefully you route them.
>
> 2. To stop noise entering into the logic ground from the I/O cabling etc.
>
> Similarly, if you isolate the grounds, you will likely increase the
> inductance
> of the signals coming out of the IO circuitry. This will cause the cables to
> radiate into the logic or to the surrounding environment.
>
> Properly shielded cable will also minimize the noise coming into the
> environment. "Proper shielding" includes a low-inductance ground connection,
> to
> the chassis if possible.
>
> 3. To provide isolation from ESD and external EMC events.
>
> >From what I can see, an "external EMC event" is the same as #2.
>
> ESD is a serious concern. You need parts that can withstand a direct ESD
> event,
> and you need to isolate them physically from the ESD source. I understand a
> separation on the order of 1mm/1000V is necessary, so if you want to avoid
> direct conduction of a 10kV ESD event, you need to guarantee 10 mm of
> separation
> of the circuitry from the source (using the enclosure to isolate the circuit
> from operator fingers, for instance). Doug Smith and his website at
> www.DougSmith.com are a great resource for both EMI and ESD.
>
> The one benefit that you will get from isolating the IO ground is that you
> are
> placing the IO circuitry in a small area. That will probably avoid the
> problem
> of shared return paths. The stitching caps will help, but really, a good,
> non-segmented ground plane is better. I suggest you design the IO circuits
> as
> though the isolation is there, but don't isolate the grounds.
>
> The structure of your board suggests another way of opening up unintentional
> loops. When a trace has to be routed from one side of the board to another,
> the
> return path gets broken (power and ground are not connected), and this will
> cause EMI. Keep your power and ground planes close together to take
> advantage of
> inter-plane capacitance. The separation depends on the edge rates of your
> signals, 10 mils *may* be sufficient, but I usually shoot for 2 mils. This
> may
> be tough on a 4-layer board, since you are (hopefully) maintaining a
> specified
> impedance and meeting a board thickness requirment. If you can't get enough
> interplane capacitance, then wherever your routing traverses through a via
> from
> one side to the other, place a capacitor close by.
>
> Engineers that I see trying to isolate grounds end up taking out the splits
> - on
> the second spin of the board, after they've failed EMC testing.
>
> Regards,
> Alan
>
> "Johnston, Ross" wrote:
> >
> > Hi Alan,
> >
> > The I/O being isolated is standard PC I/O (ie. VGA connector, serial,
> > parallel, audio). The thinking behind completely isolating the IO ground
> > from main logic ground is threefold:-
> > 1. To stop noise coming out from the logic ground onto the I/O signals.
> > 2. To stop noise entering into the logic ground from the I/O cabling etc.
> > 3. To provide isolation from ESD and external EMC events.
> >
> > I am aware that there would be an issue of traces crossing plane splits
> with
> > respect to return currents. However, I have stitching capacitors fitted
> > across the split at the point where traces cross the split (to provide a
> > path for the return current).
> >
> > My board is a standard 4 layer motherboard with tracking on the top and
> > bottom layers and power and ground in between.
> >
> > CHEERS
> >
> > ROSS
> > -----Original Message-----
> > From: Alan Hilton-Nickel [mailto:ahilton@xxxxxxxxxxxxx]
> > Sent: 06 August 2002 22:55
> > To: Johnston, Ross
> > Subject: Re: [SI-LIST] Ground plane split widths...
> >
> > Ross,
> >
> > Unless you have a desire for pain, I'd recommend *reducing* the split
> > width...to
> > zero.
> >
> > I don't know what I/O you are trying to isolate, but the return currents
> > that
> > would normally go through the ground planewill just find another route -
> > probably through your chassis. This opens up a big inductive loop. Even if
> > it
> > doesn't result in bandwidth limitation due to signal integrity violations,
> > it
> > will cause your board to radiate EMI.
> >
> > Regards,
> > Alan Hilton-Nickel
> > Transmeta Corp
> > Santa Clara, California
> >
> > "Johnston, Ross" wrote:
> > >
> > > Hi
> > >
> > > My design is basically a pc motherboard. I have isolated the I/O ground
> > from
> > > the logic ground. Currently the ground plane split is 15 thou - I am
> > > contemplating increasing this width. Should the split be kept as small
> as
> > > possible? If so - why? If the ground split was too small, wouldn't noise
> > be
> > > coupled across from each plane? What is the general consensus on this?
> > >
> > > CHEERS
> > >
> > > Ross Johnston
> > > Electronics Design Engineer,
> > > Core Electronics Group,
> > > Lifecycle GST,
> > > NCR FSG (Scotland) Ltd,
> > > Discovery Centre 2nd Floor West,
> > > 3 Fulton Road
> > > Dundee,
> > > Scotland DD2 4SW
> > > Tel: +44 (0)1382 592920 Direct Dial
> > > Fax: +44 (0)1382 591089
> > > email: ross.johnston@xxxxxxxxxxxxxxxx
> > >
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