[SI-LIST] Re: Ground bounce issue in FPGA?
- From: "Ken Cantrell" <Ken.Cantrell@xxxxxxxxxxx>
- To: <cbobek@xxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Thu, 17 Jan 2002 09:34:10 -0700
Chris,
Not familiar with the Altera part, but I have successful implementations
with the Xilinx 6M gate parts. The first thing I thought of when I read
your e-mail was routing with respect to crosstalk spacing. A volt is an
astounding amount of crosstalk. Without getting into too much detail have
you:
1. Calculated the charge storage requirements per bank (power supply
bypass, local bypass, high frequency)?
2. Do you know the maximum distance (per frequency range) the bypass caps
can be from the power pins?
3. Redone you power supply bypass calcs at 2% supply regulation instead of
5% or 10%?
4. Sim'd or cal'd your crosstalk spacing?
5. Terminated your lines correctly?
6. Accounted for mode effects on your microstrips?
100 nF caps could be inductive at your frequency of operation, and/or not
have enough storage capacity. You may need multiple caps of graduated
sizes.
Where are the clock traces routed? Keep them far away from the I/0 and PLL.
On (8)- doesn't make any sense - therefore driver type is probably not the
problem, and that ground bounce is not the dominant issue.
Look at the period on the clock and see if you have any phase differences.
If so, one typical cause is inadequate power supply bypassing letting the
low frequency noise get injected into the PLL. This would give you
aperiodic issues when the sums come together at the wrong time, and might
not be detected unless observed over an extended time frame.
If some of the basic layout issues have been accounted for and you still
have the problem, it's usually something in your FPGA logic. In fact, the
majority of the time, even on poorly laid out boards, it's usually something
in the logic. One thing that supports this is the multiplicity of issues.
Fix the logic and the problems go away.
KISS:
Check line spacing/routing for adequate crosstalk spacing. If that is OK, I
would concentrate on the implementation, and consider the potpourri of
anomalies as symptomatic of an incorrect implementation.
Ken
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Chris Bobek
Sent: Wednesday, January 16, 2002 5:29 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Ground bounce issue in FPGA?
Hi,
I have an Altera APEX 20K160E in a 484pin BGA package on a board. I
have 4 POS-PHY busses (two in, two out) and a 100bit ZBT SRAM bus on the
FPGA. When I run random, full-rate traffic through the board with a
fan, I can run error free for several days. If I take away the fan, the
case temperature ends up at 60degrees C (well within 85degree spec), yet
I receive several errors per second. I tried recompiling the code to
try to get the Fmax up, which it did, however I got errors with and
without the fan. After recompiling several other times, I get different
error rates with and without the fan. Finally, I compilied an image
without SRAM (leaving 4 PL3 busses) and ran overnight without errors and
without a fan.
Here are some facts:
1) The internal resources are only 30% utilized.
2) All external timing on the FPGA, SRAM, PL3 chips, etc. have high
measured margins, with and without fan.
3) I've tried images with/without the internal PLL enabled. Similar
results.
4) If I apply traffic with mostly all 1's (except for CRC), I run error
free without fan.
5) I have 1 .1uF cap per pin, directly under each power pin (I used
via-in-pad to fit them underneath). Plus, several bulk caps surrounding
the BGA.
6) I did not add any programmable grounds (wish I did).
7) I looked at a static, active-high output on the FPGA and noticed
about a 1V negative spike (dips to ~2.3V) coincident with the clock
period. Similar is true for active-low output (rises to ~1V). These
spikes never showed up on other signals that I was doing timing on.
8) I've tried different output drivers (LVTTL, LVCMOS). LVCMOS had
lower errors, but higher ground bounce! Why would that be?
9) I've tried slow slew rate and I get the same mixed results...
Of course, I suspect ground bounce is an issue. Are there any other
measurements I can make? Are there any possible solutions or ideas
short of choosing a larger part and making every other pin a ground?
Sorry for the long message, this has been one hairy problem!
Thanks,
Chris
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