[SI-LIST] Re: GND vs Power as reference
- From: "shengli07 ." <shengli.lin.sl@xxxxxxxxx>
- To: scott@xxxxxxxxxxxxx
- Date: Wed, 2 Oct 2013 18:42:33 -0700
Hi Brad,
Thanks for your detailed reply. The original post is about the stripline
with power or ground as reference. I'd like just to point out the trace
characteristic does not depend on the DC voltage level of the reference
plane.
Changing the reference plane along the signal path is another problem. Even
both ref planes are so called 'ground', for example, gnd1 and gnd2, if the
two 'ground' are not decoupled correctly, there is still ref path
discontinuity. As you said, SI and PI can't be separated in this case. A
good PI design should also take the return current path into consideration.
For changing the ref plane from package to PCB, we have both DDR3 and high
speed serdes work well by the careful design. Extra thoughts is needed, but
it is still doable.
Shengli Lin
On Wed, Oct 2, 2013 at 5:51 PM, Scott McMorrow <scott@xxxxxxxxxxxxx> wrote:
> Jeff,
> Let me be crystal clear. The following statement of yours is dead wrong:
>
> "For the stackups I've dealt with, "ground" and "power" planes on the PCB
> have such low impedance between them that they are ---- essentially ----
> the same for high speed signaling reference. "
>
> it just ain't true. I can measure Dk and Df of a dielectric cavity by
> passing a single-ended or differential via through two ground planes with
> 30 micron dielectric thickness that are stitched with ground vias. Float a
> plane or use a power plane and It gets quite interesting with vias passing
> through.
>
> Here's a quick experiment for you to perform. Create a board with multiple
> traces that start off referenced to ground and then transition through vias
> to power reference and then back again. Also provide probe points for
> power and ground on each side. Take a power/ground plane pair and perform
> a transfer impedance measurement from one side to the other with a VNA.
> Look at the impedance profile and note where the peaks are. Now make a
> crosstalk measurement from one trace to another. Look at the peaks.
>
>
> Regards,
>
> Scott
>
>
> On Wed, Oct 2, 2013 at 8:33 PM, Scott McMorrow <scott@xxxxxxxxxxxxx>
> wrote:
>
> > Jeff
> >
> > Placing a signal on a power layer implies changing reference layers in
> > most every case, otherwise, how do you end up on that layer in the first
> > place? Measuring a power plane referenced signal with external equipment
> > or probes requires a discontinuous return path from ground to power,
> > otherwise, what is the point? There are multiple places where this
> > reference change can occur, here are just a few.
> >
> > 1) going from a PCB through a connector, such as a PCIe connector where
> > signals passing through the connector are ground referenced.
> >
> > 2) going from a ground referenced package to a power referenced trace on
> a
> > PCB.
> >
> > 3) going from a power referenced microstrip through vias to a ground
> > referenced stripline.
> >
> > 4) going from ground referenced microstrip through vias to a power
> > referenced microstrip or stripline.
> >
> > 5) going from ground referenced microstrip through vias to a power/ground
> > referenced stripline.
> >
> > 6) going from a ground referenced die to a power referenced microstrip or
> > stripline.
> >
> > 7) going through a connector where one board has traces referenced to
> > power and the other has traces referenced to ground.
> >
> > etc ...
> >
> > In all of these cases there is a discontinuous instantaneous ground
> return
> > path. In all of these cases higher crosstalk occurs. In all of these
> > cases uncontrolled resonances will most definitely occur. Whether these
> > cause system issues is a matter of geometry, magnitude, and containment.
> >
> >
> > regards,
> >
> > Scott
> >
> >
> >
> > On Wed, Oct 2, 2013 at 7:47 PM, Loyer, Jeff <jeff.loyer@xxxxxxxxx>
> wrote:
> >
> >> Nowhere did I say that changing references was never a problem. Please
> >> read my original posting again. I only shared my experiences. I would
> >> encourage you to take a few breaths before sending out rude e-mails,
> >> probably reducing your reputation more than mine.****
> >>
> >> ** **
> >>
> >> *Jeff Loyer*
> >>
> >> ** **
> >>
> >> *From:* Scott McMorrow [mailto:scott@xxxxxxxxxxxxx]
> >> *Sent:* Wednesday, October 02, 2013 4:16 PM
> >> *To:* Loyer, Jeff
> >> *Cc:* si-list@xxxxxxxxxxxxx
> >> *Subject:* Re: GND vs Power as reference****
> >>
> >> ** **
> >>
> >> Jeff****
> >>
> >> ** **
> >>
> >> A VNA or accurate 3D frequency domain field solver result will tell you
> >> whether a design works or not, if you know where to look, and how to
> take
> >> measurements that measure what you mean to measure. Where I take issue
> >> with you, Jeff, is that your words imply that changing references is
> not a
> >> problem, which, when I think about it, should make me happy, since it
> means
> >> more business for me. ****
> >>
> >> ** **
> >>
> >> Not all power referenced signals will fail, but the probability of a
> >> problem is astronomically larger for designs that switch from ground
> >> referenced signals to power referenced signals and back. The issues
> can
> >> be seen with differential and common mode coupling, and show up usually
> >> with resonance peaking. Resonances occur that are dictated by the
> >> dimensions of the power plane, and location of bypass capacitors and
> ground
> >> vias. ****
> >>
> >> ** **
> >>
> >> The more signals that cross the "split", the more noise injected and
> >> either available as crosstalk to other signals, or just plain noise on
> the
> >> power plane. Since the power plane structure is susceptible to common
> mode
> >> resonances, it is also susceptible to common mode coupling from skewed
> >> signals, which just makes matters even worse. And if, as it is often the
> >> case, that power plane is adjacent to the top or bottom layer, you've
> built
> >> a wonderful excitation mechanism for a patch antenna.****
> >>
> >> ** **
> >>
> >> Many times the problem is barely perceptible to a TDR, due to the
> >> broadband nature of the instrument. What you may see is very low
> amplitude
> >> ringing, that is an indictor of a resonance, or very low levels of
> >> crosstalk. Lets say that you see 2 mV of crosstalk between one
> aggressor
> >> and it's victim. This might seem innocuous. But if there are 10's or
> >> 100's of aggressors, the cumulative average level of crosstalk can be
> very
> >> high. The reason for this is that once you cross the split and
> reference
> >> to the power plane your return paths are now "non-local", with impact
> that
> >> spreads across the entire plane.****
> >>
> >> ** **
> >>
> >> At 25 Gbps, you better believe that there will be problems. At 10 Gbps
> >> I've diagnosed multiple systems with improper return path issues
> causing
> >> Noise, EMI, or high BER. Sometimes it's just a matter of the link
> margins
> >> that you're working with.****
> >>
> >> ** **
> >>
> >> Again, it's not the plane, it's the transition onto and off of the plane
> >> that is the issue. This is where the noise pickup or injection
> occurs.**
> >> **
> >>
> >> ** **
> >>
> >> ** **
> >>
> >> Scott****
> >>
> >> ** **
> >>
> >> ** **
> >>
> >> On Wed, Oct 2, 2013 at 5:38 PM, Loyer, Jeff <jeff.loyer@xxxxxxxxx>
> wrote:
> >> ****
> >>
> >> (Ive changed the Subject title a bit
)****
> >>
> >> I think that if I was dead wrong, no one in the entire industry would
> >> have successfully referenced a signal to power (intentionally or
> not). I
> >> can assure you that is not the case; I personally know of 1 case where
> this
> >> has happened (that design was never corrected; it ran flawlessly).
> And,
> >> in the world of 4-layer designs, Im confident that many used power as
> the
> >> reference and not all of those who did failed.****
> >>
> >> ****
> >>
> >> Yes, I tried TDRing multiple signals to check crosstalk no
> >> difference. I didnt perform a VNA analysis.****
> >>
> >> ****
> >>
> >> The interesting thing (to me) to work on is to understand when a design
> >> will fail when power is used as a reference, and when it will not. I
> >> believe this is another it depends case, not a clear black and white
> one.
> >> ****
> >>
> >> ****
> >>
> >> Another interesting aspect is to understand how a person would detect a
> >> problem. I.E., if you had 2 designs, one of which had dual (or
> power-only)
> >> referencing and one which had only ground referencing, exactly what test
> >> would unambiguously determine the difference? As I said, I made several
> >> attempts to discern a significant difference in my design(s) without
> >> success (noise on the power plane turned out to be the only smoking
> gun,
> >> directly correlated to margin reduction). If I understand Steve
> correctly,
> >> there isnt a single test available where I could measure two black
> boxes
> >> and tell which would perform better. You would have to extract
> impedances
> >> and then run simulations in order to discern the difference. Thats a
> bit
> >> scary to me (though it may be true).****
> >>
> >> ****
> >>
> >> *Jeff Loyer*****
> >>
> >> ****
> >>
> >> *From:* Scott McMorrow [mailto:scott@xxxxxxxxxxxxx]
> >> *Sent:* Wednesday, October 02, 2013 10:12 AM
> >> *To:* Loyer, Jeff
> >> *Cc:* Stephen.Greenhalgh@xxxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
> >> *Subject:* Re: [SI-LIST] Re: AW: AW: AW: Stripline reference****
> >>
> >> ****
> >>
> >> Jeff****
> >>
> >> ****
> >>
> >> Sorry, you are dead wrong. I don't disbelieve that you think the TDRs
> >> show no difference, but did you try TDRing across multiple signals to
> look
> >> for crosstalk, or use a VNA to check for resonances? Common mode on the
> >> diff pair will ping everything referenced to that power plane. And
> through
> >> the magic of common mode to differential conversion, differential
> crosstalk
> >> will be fun.****
> >>
> >> ****
> >>
> >> This is especially a problem for NEXT on received signals where the
> power
> >> level of the transmit signals is much higher than that of the received
> >> signal. Designers tend to neglect looking for skew induced margin
> >> reduction due to crosstalk. It' generally much worse than the actual
> >> energy lost through skew on insertion loss.****
> >>
> >> ****
> >>
> >> respectfully****
> >>
> >> ****
> >>
> >> Scott****
> >>
> >> ****
> >>
> >> ****
> >>
> >> On Wed, Oct 2, 2013 at 12:53 PM, Loyer, Jeff <jeff.loyer@xxxxxxxxx>
> >> wrote:****
> >>
> >> Here's my experience to-date...
> >> For the stackups I've dealt with, "ground" and "power" planes on the PCB
> >> have such low impedance between them that they are essentially the same
> for
> >> high speed signaling reference. I.E., if you TDR between them, it
> >> indicates a dead short. Similarly, if you TDR a stripline trace that
> lies
> >> between a ground and power plane, it doesn't matter which you choose as
> >> reference (or had them shorted together at the launch) - the
> >> TDR/TDT/crosstalk waveforms are identical. Even when I had microstrip
> >> traces, some of which were referenced to power and others which were
> >> referenced to ground, I could not discern any significant difference in
> the
> >> TDR waveforms whether I chose power or ground as reference (FEXT was
> >> increased slightly, and odd-even mode TDT showed slightly more
> difference).
> >> This was true for bare boards; the decoupling caps weren't in play.
> >> This is true for the designs I've investigated for this phenomenon,
> >> perhaps there are other designs/stackups which would have different
> results.
> >> On the other hand, I have experienced problems having signals referenced
> >> to a power plane for a different reason. The noise on the power plane
> has
> >> gotten injected into my signals and caused severe problems. Of course
> that
> >> noise is going to be dependent on the power plane itself (12V power
> might
> >> kill a signal while 1.8V power might work fine).
> >> Differential signals have proven to be more immune to this noise but,
> >> interestingly enough, I've had noise on a differential clock signal
> wreak
> >> havoc. We believe that the "signals" themselves weren't the problem,
> that
> >> the noise on those signals got coupled into the chip and caused
> problems,
> >> but that's only conjecture.
> >>
> >> Jeff Loyer****
> >>
> >>
> >>
> >> -----Original Message-----
> >> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx
> ]
> >> On Behalf Of Stephen Greenhalgh
> >> Sent: Wednesday, October 02, 2013 8:18 AM
> >> To: si-list@xxxxxxxxxxxxx
> >> Subject: [SI-LIST] Re: AW: AW: AW: Stripline reference
> >>
> >> I think this message is sufficiently on-topic not to be regarded as
> >> hijacking the thread. I offer my apologies in advance if others
> disagree.
> >>
> >> Clearly simulation must reflect the actual pcb as closely as possible,
> >> and whichever plane is reference in the pcb should be used in the
> >> simulation. But, in the pcb, as far as signal integrity is concerned
> which
> >> (power or ground) is the better reference plane to use? Does it matter
> >> hugely for differential (as opposed to single-ended) signalling? Does it
> >> depend on the technology used?
> >>
> >> For example, a LVPECL output stage typically has a constant current
> >> source connected to power with the switching transistors between this
> and
> >> ground. Data sheets define the voltage levels relative to ground.
> >> Terminations connect between signals and ground. So ground is the
> obvious
> >> reference plane to use.
> >>
> >> However, for CML the reverse is the case. The constant current source is
> >> connected to ground with the switching transistors between this and
> power.
> >> Data sheets define the voltage levels relative to power. Terminations
> >> connect between signals and power. So, is power the better choice for
> >> reference plane?
> >>
> >> Just as importantly, why (or why not)?
> >>
> >> Regards,
> >> Stephen
> >>
> >>
> >> -----Original Message-----
> >> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx
> ]
> >> On Behalf Of Scott McMorrow
> >> Sent: 02 October 2013 12:51
> >> To: steve weir
> >> Cc: si-list@xxxxxxxxxxxxx
> >> Subject: [SI-LIST] Re: AW: AW: AW: Stripline reference
> >>
> >> Amit
> >> For a power referenced differential pair, all the "bad" stuff happens in
> >> two places.
> >>
> >> 1) getting from the package onto the power plane reference
> >>
> >> 2) getting off the power plane reference and onto the outbound
> connector.
> >>
> >> Shorting the to ground is not even close to an approximation of this.
> If
> >> you want to model this, you have to go back into the package and to the
> >> other side of the connector where there are grounds referencing the
> signal.
> >> However (spoiler alert) your power referenced differential pair is an
> >> resonance and EMI nightmare. You might want to figure out how to
> engineer
> >> it out.
> >>
> >> We often talk about not routing over split planes. Well, your
> >> differential pair crosses two splits, one coming off the package, and
> one
> >> jumping onto the connector.
> >>
> >> good luck
> >>
> >> Scott
> >>
> >>
> >> On Wed, Oct 2, 2013 at 5:00 AM, steve weir <weirsi@xxxxxxxxxx> wrote:
> >>
> >> > Amit, no that is a bad idea. Unless the geometries are small compared
> >> > to the signal wavelengths such an approximation will be poor.
> >> >
> >> > Steve.
> >> > On 10/2/2013 1:16 AM, Amit Kumar wrote:
> >> > > Hi Gert,
> >> > >
> >> > > I messed up the question actually.
> >> > > I want to know the impact of shorting the vdd and gnd nets. The
> >> > > TX/RX
> >> > model I have is a behavioural model which does not take power into
> >> account.
> >> > > So the conventional port reference definition of dual referencing
> >> > > will
> >> > not work for me.
> >> > > So I was thinking whether it is ok to short vdd and gnd nets for
> >> > > signal
> >> > s parameter extraction?
> >> > > One problem which is obvious is that ill be ignoring the inductance
> >> > which the return path would have encountered for travelling from vdd
> >> > to gnd. Will shorting vdd gnd locally on one end give me an
> approximate
> >> result?
> >> > >
> >> > >
> >> > > Regards
> >> > > Amit Kumar
> >> > >
> >> > > Baghmane Tech park, Bengaluru
> >> > > T: + 91-80-42422526
> >> > > amit.kumar@xxxxxxxxxxx
> >> > >
> >> > >
> >> > > -----Original Message-----
> >> > > From: si-list-bounce@xxxxxxxxxxxxx
> >> > > [mailto:si-list-bounce@xxxxxxxxxxxxx]
> >> > On Behalf Of Havermann, Gert
> >> > > Sent: Wednesday, October 02, 2013 1:27 PM
> >> > > To: si-list@xxxxxxxxxxxxx
> >> > > Subject: [SI-LIST] AW: AW: AW: Stripline reference
> >> > >
> >> > > Hi Amit,
> >> > >
> >> > > it is NEVER ok to use power as a port reference in simulation
> >> > > unless,
> >> > the later Chip also uses power as reference (which I haven't seen in
> >> > high speed digital yet).
> >> > > The Pots have to be placed "close to reality". If Your chip has a
> >> > > GND
> >> > reference for signal output and you change layers in the fanout of the
> >> > package, then your port has to be placed on the Solder Land (Chip
> >> > Footprint) referencing to GND. The Power plane which is reference for
> >> > the trace on the new routing Layer will automatically become reference
> >> > to the signal that is routed in close proximity. If you then don't
> >> > provide some sort of return path for ac-return currents from Power
> >> > plane to your Ports GND reference, you will see massive ringing and
> >> > radiation, and this ringing will also be seen in reality if the return
> >> path is missing.
> >> > > If you would use PWR as the Port reference, you will not see the
> >> > > ringing
> >> > that will be there in reality.
> >> > >
> >> > > Always remember: Simulation can be a bitch as Simulation will always
> >> > give you a result, but never tells you if the result is true or wrong.
> >> > It is on you to model as close to reality as possible. If you decide
> >> > to drop features in simulation, YOU have to make sure that the result
> >> > is still usable.
> >> > >
> >> > > BR
> >> > > Gert
> >> > >
> >> > >
> >> > > ----------------------------------------
> >> > > Absender ist HARTING Electronics GmbH, Marienwerderstraße 3, D-32339
> >> > Espelkamp; Registergericht: Amtsgericht Bad Oeynhausen; Register-Nr.:
> >> > HRB 8808; Vertretungsberechtige Geschäftsführer: Dipl.-Kfm.
> >> > Edgar-Peter Düning, Dipl.-Ing. Torsten Ratzmann
> >> > >
> >> > > -----Ursprüngliche Nachricht-----
> >> > > Von: Amit Kumar [mailto:Amit.Kumar@xxxxxxxxxxx]
> >> > > Gesendet: Mittwoch, 2. Oktober 2013 07:09
> >> > > An: Havermann, Gert; si-list@xxxxxxxxxxxxx
> >> > > Betreff: RE: [SI-LIST] AW: AW: Stripline reference
> >> > >
> >> > > Hello Gert/Experts,
> >> > >
> >> > > The discussion on the stripline reference was really good. Thanks to
> >> > everyone for the contribution.
> >> > >
> >> > > I have a differential pair routed on top and bottom layer(so both
> >> > microstrip). The top layer routing has a vdd plane as reference and
> >> > the bottom routing has gnd as reference.
> >> > > I have two questions here:
> >> > >
> >> > > 1) Do you see a significant impact on performance because of
> >> > > different
> >> > reference plane on different layers.
> >> > > 2) How do we assign ports for this differential pair? Is it ok to
> >> > > assign
> >> > one side port with ground reference and other side with power
> reference?
> >> > >
> >> > > Regards
> >> > > Amit Kumar
> >> > >
> >> > > Baghmane Tech park, Bengaluru
> >> > > T: + 91-80-42422526
> >> > > amit.kumar@xxxxxxxxxxx
> >> > >
> >> > >
> >> > > -----Original Message-----
> >> > > From: si-list-bounce@xxxxxxxxxxxxx
> >> > > [mailto:si-list-bounce@xxxxxxxxxxxxx]
> >> > On Behalf Of Havermann, Gert
> >> > > Sent: Monday, September 30, 2013 1:31 PM
> >> > > To: si-list@xxxxxxxxxxxxx
> >> > > Subject: [SI-LIST] AW: AW: Stripline reference
> >> > >
> >> > > Amit,
> >> > >
> >> > > if power and GND have the same distance to the trace, then both will
> >> > > see
> >> > identical coupling and the return current that flows on the Planes
> >> > will be equal in both planes.
> >> > > The Cap I mentioned is the coupling cap between Power and GND. The
> >> > Return current on the Power plane has to go back to the signal source.
> >> > Since the Power plane has no direct DC connection to GND, you have to
> >> > establish a capacitive coupling to allow the current to flow back to
> >> GND.
> >> > The position of these caps governs the "detour" you force the return
> >> > current to flow. This means additional inductance in your path, and a
> >> > great source of crosstalk. Without Coupling caps you will create lots
> >> > of radiation as the currents will find their way "over the air".
> >> > >
> >> > > I hope this helps.
> >> > >
> >> > > BR
> >> > > Gert
> >> > >
> >> > >
> >> > > ----------------------------------------
> >> > > Absender ist HARTING Electronics GmbH, Marienwerderstraße 3, D-32339
> >> > Espelkamp; Registergericht: Amtsgericht Bad Oeynhausen; Register-Nr.:
> >> > HRB 8808; Vertretungsberechtige Geschäftsführer: Dipl.-Kfm.
> >> > Edgar-Peter Düning, Dipl.-Ing. Torsten Ratzmann
> >> > >
> >> > > -----Ursprüngliche Nachricht-----
> >> > > Von: Amit Kumar [mailto:Amit.Kumar@xxxxxxxxxxx]
> >> > > Gesendet: Freitag, 27. September 2013 13:20
> >> > > An: Havermann, Gert; si-list@xxxxxxxxxxxxx
> >> > > Betreff: RE: [SI-LIST] AW: Stripline reference
> >> > >
> >> > > Hello Gert,
> >> > >
> >> > > What if power and ground layers are equidistant from the signal
> layer?
> >> > > Also, can you explain what do you mean by the position of the cap?
> >> > >
> >> > > Regards
> >> > > Amit Kumar
> >> > >
> >> > > Baghmane Tech park, Bengaluru
> >> > > T: + 91-80-42422526
> >> > > amit.kumar@xxxxxxxxxxx
> >> > >
> >> > > -----Original Message-----
> >> > > From: si-list-bounce@xxxxxxxxxxxxx
> >> > > [mailto:si-list-bounce@xxxxxxxxxxxxx]
> >> > On Behalf Of Havermann, Gert
> >> > > Sent: Friday, September 27, 2013 4:37 PM
> >> > > To: si-list@xxxxxxxxxxxxx
> >> > > Subject: [SI-LIST] AW: Stripline reference
> >> > >
> >> > > It all depends on the position of Coupling caps, the distance to
> >> > > each
> >> > plane and the speed of your signal.
> >> > > If you simulate, you have to take the position of the caps into
> >> > > account,
> >> > or at least leave the power plane floating at each port. The model
> >> > must be as close to reality as possible, thus only connections between
> >> > planes that are really there should be used in simulation. And the
> >> > right boundary has to be used as it has massive influence on the
> >> results.
> >> > >
> >> > > BR
> >> > > Gert
> >> > >
> >> > >
> >> > > ----------------------------------------
> >> > > Absender ist HARTING Electronics GmbH, Marienwerderstraße 3, D-32339
> >> > Espelkamp; Registergericht: Amtsgericht Bad Oeynhausen; Register-Nr.:
> >> > HRB 8808; Vertretungsberechtige Geschäftsführer: Dipl.-Kfm.
> >> > Edgar-Peter Düning, Dipl.-Ing. Torsten Ratzmann
> >> > >
> >> > > -----Ursprüngliche Nachricht-----
> >> > > Von: si-list-bounce@xxxxxxxxxxxxx
> >> > > [mailto:si-list-bounce@xxxxxxxxxxxxx]
> >> > Im Auftrag von Jason wuc
> >> > > Gesendet: Freitag, 27. September 2013 12:55
> >> > > An: si-list@xxxxxxxxxxxxx
> >> > > Betreff: [SI-LIST] Stripline reference
> >> > >
> >> > > Hello Experts,
> >> > > I need your help.
> >> > >
> >> > > I am extracting s-parameter of some strupline traces. These traces
> >> > connect two flip chips on board and are routed between power and
> >> > ground plane where power is upper plane and ground is lower plane I
> >> > am in doubt that whether I should take ground/power as reference or
> >> > both planes as reference while assigning ports.
> >> > >
> >> > > Please reply.
> >> > >
> >> > > Jason
> >> > >
> >> > >
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> >> > >
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> >> > --
> >> > Steve Weir
> >> > IPBLOX, LLC
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> >> --
> >>
> >> Scott McMorrow
> >> Teraspeed Consulting Group LLC
> >> 16 Stormy Brook Rd
> >> Falmouth, ME 04105
> >>
> >> (401) 284-1827 Business
> >>
> >> http://www.teraspeed.com
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> >> Teraspeed® is the registered service mark of Teraspeed Consulting Group
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> >> http://www.qsl.net/wb6tpu****
> >>
> >>
> >>
> >> ****
> >>
> >> ****
> >>
> >> --
> >>
> >> Scott McMorrow
> >> Teraspeed Consulting Group LLC
> >> 16 Stormy Brook Rd
> >> Falmouth, ME 04105
> >>
> >> (401) 284-1827 Business
> >>
> >> http://www.teraspeed.com
> >>
> >> Teraspeed® is the registered service mark of
> >> Teraspeed Consulting Group LLC****
> >>
> >>
> >>
> >> ****
> >>
> >> ** **
> >>
> >> --
> >>
> >> Scott McMorrow
> >> Teraspeed Consulting Group LLC
> >> 16 Stormy Brook Rd
> >> Falmouth, ME 04105
> >>
> >> (401) 284-1827 Business
> >>
> >> http://www.teraspeed.com
> >>
> >> Teraspeed® is the registered service mark of
> >> Teraspeed Consulting Group LLC
> >>
> >> ****
> >>
> >
> >
> >
> > --
> >
> > Scott McMorrow
> > Teraspeed Consulting Group LLC
> > 16 Stormy Brook Rd
> > Falmouth, ME 04105
> >
> > (401) 284-1827 Business
> >
> > http://www.teraspeed.com
> >
> > Teraspeed® is the registered service mark of
> > Teraspeed Consulting Group LLC
> >
> >
> >
> >
> >
> > --
> >
> > Scott McMorrow
> > Teraspeed Consulting Group LLC
> > 16 Stormy Brook Rd
> > Falmouth, ME 04105
> >
> > (401) 284-1827 Business
> >
> > http://www.teraspeed.com
> >
> > Teraspeed® is the registered service mark of
> > Teraspeed Consulting Group LLC
> >
> >
> >
>
>
> --
>
> Scott McMorrow
> Teraspeed Consulting Group LLC
> 16 Stormy Brook Rd
> Falmouth, ME 04105
>
> (401) 284-1827 Business
>
> http://www.teraspeed.com
>
> Teraspeed® is the registered service mark of
> Teraspeed Consulting Group LLC
>
> ------------------------------------------------------------------
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>
>
>
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List forum is accessible at:
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