[SI-LIST] Re: GND vs Power as reference
- From: Scott McMorrow <scott@xxxxxxxxxxxxx>
- To: Hermann Ruckerbauer <Hermann.Ruckerbauer@xxxxxxxxxxxxx>
- Date: Thu, 3 Oct 2013 15:00:14 -0400
Hermann
For frequencies above about 1 GHz, stitching caps do not help. Just
compute the impedance of the mounted inductance. 400 pH mounted
inductance would be pretty aggressive for a capacitor mounted on the top
layer and attached to and L2/L3 ground/power pair, which would have an
impedance of 2.5 ohm at 1 GHz, 25 ohm at 10GHz, which is hardly a short
circuit.
The solution is to contain the power plane between ground planes, creating
a shorted super-cavity.
Scott
On Thu, Oct 3, 2013 at 2:48 PM, Hermann Ruckerbauer <
Hermann.Ruckerbauer@xxxxxxxxxxxxx> wrote:
> Hello Stefan,
>
> the stitching cap is an interesting question .. (at least for me ..)
> Up to a discussion with Eric Bogatin I also was telling people to place
> a cap for AC current return there ..
>
> Unfotunatelly Eric did a short calculation (he is MUCH better in theory
> than I am...) and with the involved inductances he came to the
> conclusion that they do not help for the desired frequency range ...
> So currently I have no real solution what to tell people in such a case ..
>
> Maybe I missunderstood Eric and maybe he can comment if he is listening ..
>
> Hermann
>
>
>
> EKH - EyeKnowHow
> Hermann Ruckerbauer
> www.EyeKnowHow.de
> Hermann.Ruckerbauer@xxxxxxxxxxxxx
> Itzlinger Strasse 21a
> 94469 Deggendorf
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>
> schrieb Stefan Milnor:
> > Sometimes you just have to use the two different planes. Do the experts
> > believe in the "stitching cap" methodology? Where you take care to have
> > a capacitor connecting the two planes next to or near the via that
> > transitions the signals from one layer to another. Along with a liberal
> > sprinkling of these stitching caps in the route areas in question.
> >
> > -----Original Message-----
> > From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
> > On Behalf Of Orin Laney
> > Sent: Thursday, October 03, 2013 10:19 AM
> > To: bradb@xxxxxxxxxxx; gnuarm.2006@xxxxxxxxx; si-list@xxxxxxxxxxxxx
> > Subject: [SI-LIST] Re: GND vs Power as reference
> >
> > For DC, power and ground planes are connected through the power supply.
> > The impedance of a well regulated supply is close to zero (milliohms).
> > As frequency increases, the PDN capacitance implementation (distributed
> > and
> > discrete) determines what impedance is seen by the various loads.
> > Planes that are "not connected" can only serve purposes other than power
> > distribution. That sounds like a special case not really applicable to
> > the discussion.
> >
> > Orin
> >
> > -----Original Message-----
> > From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
> > On Behalf Of Bradley Brim
> > Sent: Thursday, October 03, 2013 10:01 AM
> > To: gnuarm.2006@xxxxxxxxx; si-list@xxxxxxxxxxxxx
> > Subject: [SI-LIST] Re: GND vs Power as reference
> >
> > Hi Rick,
> >
> > Current flows in loops, even at DC.
> > For case 2, port 1 pulls current from the top plane and pushes it into
> > the top microstrip. Current flows down through the via into the bottom
> > microstrip to port 2, where it then pushed into the bottom plane.
> > How does current get from the bottom to the top plane for form a loop?
> > If the planes are not connected then there is no DC path and the
> > measurement/simulation is of an open circuit at low frequency. As
> > frequency increases there is a displacement current through the plane
> > capacitance.
> > This is a series capacitance in the return path.
> >
> > Build it and measure it, or (properly) simulate it, and it will behave
> > in the manner I describe.
> > For this simple design you can even model it with circuit simulation if
> > you do not use a common node for the two port references and insert a
> > capacitor in the return path. This simple circuit model does not include
> > resonance effects of the parallel plate cavity but works for this simple
> > design at frequencies where the planes behave only as a capacitor.
> >
> > -------- ---- ----- ---- --------
> > -----| Port 1 |-----| MS |-----| Via |-----| MS |-----| Port 2 |-----
> > | -------- ---- ----- ---- -------- |
> > | |
> > | ---------- |
> > |------------------------------| C_planes |--------------------------
> > _|_ ----------
> > -
> >
> > Cheers,
> > -Brad
> >
> > P.S. the ASCII graphics are logical in fixed pitch fonts
> >
> >
> >
> > -----Original Message-----
> > From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
> > On Behalf Of Rick Collins
> > Sent: Wednesday, October 02, 2013 4:33 PM
> > To: si-list@xxxxxxxxxxxxx
> > Subject: [SI-LIST] Re: GND vs Power as reference
> >
> > That is a very interesting analysis, but in case
> > 2 I'm not at all clear how the lack of a DC connection between the two
> > power planes makes any difference. The behavior of the signal trace at
> > DC is not at all affected by the proximity of the metal planes. So why
> > bother to mention that?
> > Are you talking about the DC behavior because that is the behavior at
> > low frequency up to the point where the distributed capacitance becomes
> > significant? Even then, the coupling between the two power planes in
> > case 2 would seem to be easily as significant as the coupling between
> > the signal trace and the power plane at any frequency. I'm not clear on
> > what you are trying to indicate. I get the impression that you feel the
> > trace is impacted by proximity to the power plane at a lower frequency
> > than the power planes will affect each other.
> >
> > I have been led to believe that power and ground planes couple in such a
> > way that their influence on a signal at relevant frequencies is the
> > same. But then it was pointed out to me that concept only holds up to
> > the low GHz.
> > Above that the coupling between the two planes changes and they no
> > longer have an equivalent impact on the signal, at least not when the AC
> > return current is expected to cross between them because of an
> > interruption in one plane. But that is a different issue.
> >
> > Am I missing something here?
> >
> > Rick
> >
> >
> > At 07:16 PM 10/2/2013, Bradley Brim wrote:
> >> Hello Shengli,
> >>
> >> SUMMARY:
> >> Your return path may seem to be well defined locally, but your
> >> circuit's behavior is affected by how your source references hook to
> >> your circuit, the quantity and location of stitching vias and decaps
> >> amongst planes, distributed capacitance between planes, etc.
> >>
> >> DETAILS:
> >> Case 1: Examine a 3-layer board with a microstrip on the top and the
> >> bottom and a metal plane in the middle. You have a length of trace on
> >> each side and a via to connect the two traces. Assume you have two
> >> ports matched to the impedance of the traces with each port referenced
> >> to the common plane in the middle. At low frequency you see a thru line
> >> in the measurement/simulation. At high frequency you see the delay of
> >> the trace and parasitics of the pad/via geometry.
> >>
> >> P1+ -----------
> >> |
> >> P1- --------- | --------- P2-
> >> |
> >> ----------- P2+
> >>
> >> Case 2: Now go to a 4-layer board by adding another plane in the
> >> middle. The via is longer by the thickness of the added layer. Now port
> >> 1 is referenced to the top plane and port 2 is referenced to the bottom
> >> plane. Do your measurements/simulations look the same? NO!
> >> There is no direct connection between the two planes, therefore there
> >> is no DC path and you have a series capacitor in your return path. At
> >> low frequency you will see an open circuit (i.e.
> >> mag(S21)=0). Until the frequency is high enough that this series
> >> capacitor has very low impedance you will see significant effect. If
> >> your board is large then this capacitance will be large and you will
> >> see non-zero S21 at well below your circuit's switching frequencies.
> >> However, your two planes may resonate and at certain frequencies you
> >> will notice a high impedance at the via location manifested in the
> >> results as an unexpectedly small S21 value. If you add decaps between
> >> the two planes you can lower the frequency at which yo
> >> u begin to see transmission for this 4-layer board and you also
> >> reduce the likelihood of plane resonances affecting your intended thru
> >> signal but you do not eliminate the DC open circuit.
> >>
> >> P1+ -----------
> >> |
> >> P1- --------- | ---------
> >> |
> >> --------- | --------- P2-
> >> |
> >> ----------- P2+
> >>
> >> Case 3: Add a via from the bottom layer to the top plane (not
> >> connecting to the bottom plane) near the location of port 2 to enable
> >> referencing to the top plane. You now have a thru connection at DC.
> >> Your return path is remote from the via, which creates a larger loop
> >> than the return current through high frequency effects of distributed
> >> capacitance near the via or via-local decaps. This implies a complexity
> >> in the frequency response (a larger and frequency-dependent series
> >> inductance at low
> >> frequency) as you transition from this new direct "DC" return path to a
> >> more via-local "AC"
> >> return path of current between top and bottom planes in the form of
> >> displacement current through plane capacitance or through decaps. You
> >> no longer have the series capacitance in the return path as for Case 2
> >> but you have a more complex response than for Case 1.
> >>
> >> P1+ -----------
> >> |
> >> P1- --------- | --------- P2-
> >> | |
> >> --------- | ------- |
> >> | |
> >> ----------- P2+
> >>
> >> Again, your return path may seem to be well defined locally, but your
> >> circuit's behavior is affected by how your source references hook to
> >> your circuit, the quantity and location of stitching vias and decaps
> >> amongst planes, distributed capacitance between planes, etc. How much
> >> is it affected? "It depends" :-) SI and PI are inseparable.
> >>
> >> Best regards,
> >> -Brad
> >>
> >>
> >> P.S. You should well understand how you simulation tool works.
> >> (1) If it assumes ideal return paths, as circuit simulation based
> >> techniques often do, then case
> >> 2 and 3 are not handled properly.
> >> (2) If you apply a MoM simulator and avoid meshing the planes (by
> >> assuming they are infinite in lateral extent to enable only meshing the
> >> via antipad), then there is an infinite capacitance amongst all planes
> >> and you ignore critical aspects of non-ideal power delivery in your EM
> >> simulation.
> >> (3) If you short together power and ground in your EM simulation to
> >> form a common reference at/near your port you provide a deterministic
> >> path for current to get from one net to the other but you are changing
> >> how your design behaves because those nets are not really shorted at
> >> this location.
> >>
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--
Scott McMorrow
Teraspeed Consulting Group LLC
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