[SI-LIST] Re: Fwd: vgs stress in digital cmos process
- From: Christopher Jakubiec <Christopher.Jakubiec@xxxxxxx>
- To: Robert.Kezer@xxxxxxxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Thu, 10 Jul 2003 08:48:07 -0700 (PDT)
Your analysis is correct, however high electric fields at the drain cause not
only hot electrons, but electron hole pairs due to the high energy particle
collisions. This in turn can inject electrons into the gate oxide (as you
stated), but can also generate hole current in the substrate that I have been
able to measure. On the gate side, tunneling will occur along with charge
trapping/de-trapping in the gate oxide. If enough charge traps are created and
a path from one side of the oxide to the other is formed, then essentially the
oxide has been ruptured. All of these conditions on the gate oxide can
modulate
the threshold voltage.
> From: Robert Kezer <Robert.Kezer@xxxxxxxxxxxxx>
> To: "'Christopher.Jakubiec@xxxxxxx'" <Christopher.Jakubiec@xxxxxxx>,
si-list@xxxxxxxxxxxxx
> Subject: RE: [SI-LIST] Re: Fwd: vgs stress in digital cmos process
> Date: Thu, 10 Jul 2003 11:39:04 -0400
>
> For high Vds voltage. It has been my experience that since CMOS devices are
> surface
> transport devices that hot electrons are pulled into the gate oxide and not
> the
> substrate. When these electrons hit the gate oxide they may dislodge one
> of the atoms. This changes the threshold voltage of the device slightly.
> Over
> time the threshold will change enough to cause a fault.
>
> For high Vgs, the gate oxide will short through when a large enough electric
> field
> has been placed acrossed it. Before this though, tunneling will occur.
>
> Bob
>
> -----Original Message-----
> From: Christopher Jakubiec [mailto:Christopher.Jakubiec@xxxxxxx]
> Sent: Thursday, July 10, 2003 11:32 AM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: Fwd: vgs stress in digital cmos process
>
>
> Hi,
>
> High voltage on either the gate (Vgs) or the drain (Vds) can cause reliabil=
> ity=20
> problems in the 0.18um CMOS process. There are two seperate physical issue=
> s=20
> taking place here though. Raising the voltage on the gate (Vgs) increases =
> the=20
> electric field across the gate-oxide-channel/bulk. So, the stress in this =
> case=20
> is on the gate oxide layer, and the extent of the stress depends on the oxi=
> de=20
> thickness. Thinner oxides will be experience more stress for a given gate=
> =20
> voltage. An over-stressed oxide can rupture, cause significant leakage, an=
> d=20
> ultimatley lose gate control. On the drain node, raising the voltage (Vds)=
> can=20
> generate high electric fields near the drain. The effect of high electric=
> =20
> fields near the drain is hot carrier injection into either or both the gate=
> =20
> oxide and the substrate. This can cause significant substrate current, and=
> can=20
> also effect the threshold voltage of the transistor. If the channel length=
> is=20
> short, this can also open up a series of short channel effects. Generally=
> =20
> people are more interested in how high they can drive the drain voltage to=
> =20
> obtain maximum speed/drive current, and thus reliablilty concerns are focus=
> ed=20
> there. Be aware if you are using thin gate oxides with higher than nominal=
> =20
> voltages on the gate, this can be problematic as well.
>
> Chris Jakubiec
> Product Engineer
> Sun Microsystems
>
>
> >=20
> > HI, experts:
> > =20
> > I want to know that in 0.18um Digital CMOS process, major stress concern =
> is=20
> Vgs or Vds?
> > =20
> > i.e., if 1.8v NMOS's Vgs is higher than 1.8v, such as 1.9 or 2.2, will th=
> at=20
> cause reliability problem?
> > =20
> > According to one paper, only Vds higher than 1.8v will cause reliability=
> =20
> issue. The margin for Vgs will be much higher.
> > =20
> > Can any people familiar with silicon explain it for me? TSMC data may be =
> used=20
> for reference.
> > =20
> > Thanks!
> > =20
> > BH
> > (If you have received , please ignore, thanks)
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