[SI-LIST] [Fwd: Re: Re: package SSN model accuracy requirements]
- From: Chuck Yuan <xyuan@xxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Mon, 04 Apr 2005 09:51:10 -0700
>
> Hi, Larry.
>
> I thought your post is excellent! Our experience is similar to yours
> in that it is possible to build "dirt" simple models to achieve great
> hardware to model correlations. Some of our results were published in a
> recent DesignCon 2004 paper.
>
> I would add my "two cents" to the already long discussions as in the
> following:
>
> A. Accuracy is an abstract term.
> One may refer to different things even using the same term. For
> example, is accuracy referring to the worst case peak to peak noise?
> Where is this noise measured, at package pin relative local ground or at
> transistors relative its local ground or global ground? The accuracy
> could also be refer to the ability to predict the voltage and timing
> loss of the driver/receiver in the presence of power/ground noise. If we
> debate about the accuracy, it would be good if we can be specific
> about what we mean in terms of accuracy.
>
> B. Getting correct current information on the supply is critical.
> Depending on how the I/O is designed, different circuits may reside
> on different rails. SSN is commonly referring to the output drivers on a
> supply which we refer to as VDDIO. However, this is hardly the only
> thing that generates noise. The logic circuits such as clock tree that
> are before output drivers also generate noise. These circuits typically
> are located a separate rail that we call VDD. It is part of the SSN!
> There are coupling or interactions among VDD and VDDIO. Without knowing
> the precise amount of current going to different supply rails, it would
> be hard to get accurate results. Your example is a great case
> illustrating this point!
>
> C. Finding the worst case data pattern is important for SSN predictions
> A typical PDN model in frequency domain shows a few resonances. L
> di/dt induced noise is typically at high frequency but it may not the
> worst case. The most critical case could be the medium frequency range
> that is heavily dependent on the data patterns. The ability to excite
> the worst case resonance is paramount.
>
> D. The ability to predict what "circuits" see is very important
> Since it is not easy to directly probe on the silicon, one often has
> to resort to monitor noise on the package pin and project the noise at
> the circuits. Having an accurate passive PDN model would be essential
> for this goal. It is also possible to design on chip noise monitor for
> hardware to model correlations. Of course, such noise monitor is only
> possible for testchips not for products.
>
> E. Understanding the circuit to noise sensitivity is important.
> We typically use the metric "ps/mV" to measure the circuit
> sensitivity. Different circuits from different vendors obviously have
> different circuit sensitivity. What is acceptable in terms of noise for
> one vendor may not be acceptable to others. Knowing this information
> would help designer to judge the impact of the noise on system performance.
>
> The above issues I outlined are somewhat different from what are
> already posted. Hopefully, they are useful to those who are interested
> in the topic.
>
> Regards,
>
> -Chuck Yuan
> Rambus Inc.
>
> Larry SMITH wrote:
> > Arpad and all - There has been a lot of good discussion on this thread
> > concerning the accuracy of SSN models. Many types of models have been
> > discussed including SPICE, IBIS, Behavioral and Macro. In most cases, I
> > believe that accuracy refers to the output voltage or impedance vs time.
> >
> > But for the traditional SSN problem, the issue is really current because
> > current is the important variable for L*di/dt simulation. It is
> > extremely important that the currents in the Vdd and Ground branches of
> > the model are accurate, as well as the output current. I fear that this
> > is sometimes overlooked in SSN model discussions. Generally, the
> > silicon SSN model will be connected to package inductance matrices,
> > power planes and/or transmission lines as well as on-chip, on-package
> > and on-pcb decoupling capacitance for the SSN simulation. The most
> > important properties of the silicon SSN model are the branch currents,
> > which of course are dependent upon the node voltages surrounding the model.
> >
> > I remember one particular SSN analysis where I was dealing with power
> > planes. All current for the driver had to enter and leave through the
> > power planes or transmission line traces. Unfortunately, the silicon
> > SPICE model that I was using did not conserve current. The sum of the
> > current into the VDD, Ground and driver-output nodes was not zero and
> > Kirchhoff's current law was violated by the SPICE model! There was no
> > zero or ground node reference in the portion of the model that was
> > visible, so the leakage was buried down in the process parameters where
> > I had no access.
> >
> > My simulation took some wild voltage excursions as current tried to
> > sneak into and out of the driver by some path other than the power
> > planes. My solution was to build a dirt simple model from time varying
> > resistors, much simpler than a model developed from IBIS data. I got
> > good model to hardware correlation even though most people would have
> > said that my SSN model was not at all accurate.
> >
> > The point of all this is that you have to carefully examine the system
> > where your SSN models will be used. The system is likely to be very
> > sensitive to some model characteristics and not to others. I'm sure my
> > SPICE transistor model was very accurate for output voltage vs time and
> > maybe even drive strength. But it was not usable in the simulation that
> > I was trying to do.
> >
> > regards,
> > Larry Smith
> > Sun Microsystems
> >
> >
> >
> > Muranyi, Arpad wrote:
> >
> >>Chris,
> >>
> >>The same is also true for SPICE! You are putting your faith
> >>into those engineer's hands who write your process files. And
> >>the average circuit designer usually has no clue for how to
> >>correct a bad transistor process file. Many times they don't
> >>even know where the limitations of the model are that they are
> >>using...
> >>
> >>Having worked for the same company I work for, you should
> >>remember some of the horror stories from those good old days
> >>when the IV curve of certain transistor models were on the
> >>order of 2-3x away from measurements... And what did we do
> >>to get a quick fix? We tweaked the .OPTIONS and did tricks
> >>with other simulation parameters because the process files
> >>were not going to change any time soon. (Good luck doing
> >>this independently for the N and P transistors). But I
> >>think I may have already said too much, so I will stop
> >>right here.
> >>
> >>Arpad
> >>=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
> >>=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
> >>=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
> >>
> >>-----Original Message-----
> >>From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] =
> >>On Behalf Of Chris Cheng
> >>Sent: Wednesday, March 16, 2005 3:31 PM
> >>Cc: si-list@xxxxxxxxxxxxx
> >>Subject: [SI-LIST] Re: package SSN model accuracy requirements
> >>
> >>
> >>...
> >>=20
> >>d) Which brings back my fundamental problem with behavioral modelling. I
> >>really don't know what the answers in c) should be but none of them =
> >>seems
> >>straight forward enough to me that the Joe app engineer can crank out in =
> >>the
> >>very near future. Anytime you have to attempt to deviate from the =
> >>original
> >>design flow of the Si houses (which I presume is dominated by SPICE), =
> >>you
> >>are putting faith in the app engineers who, up to now, can not even =
> >>abstract
> >>out a standard to help me predict a simple SSO problem other than using
> >>encrypted HSPICE.
> >>=20
> >>What do you think ?
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