[SI-LIST] Fwd: Re: Copper pours on a 2-layer PCB
- From: "Carlos Toro" <torocar@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Mon, 13 Nov 2006 19:06:14 -0500
Hello you all. Unfortunelly, the local company which we pretend to hire for
manufacturing our board just makes 2 layer boards (max). Probably our design
wouldn't require more than that but since it is our the first time we
pretend to hire the services of such a company some doubts have come up.
The PCB engineers have assigned both the TOP and BOTTOM layers as routing
layers (not plane layers, since there are only two layers to work on). The
TOP layer is being used for routing as many signals and +5V power traces as
possible while in the BOTTOM layer a copper pour attached to GND is to be
placed (there are some spots where signal traces partially go in the BOTTOM
layer since sometimes they cross, however, one of the goals is to chop the
BOTTOM layer as less as possible). The PCB is basically a development board
prototype for a microcontroller. There are not high power components
involved.
*Now, these are the doubts that have come up through the layout process and
I would like you to kindly give me your advice on:*
**
*1. Should a copper pour attached to +5V be placed in the TOP layer?. An
effort has been put on for distributing both power and GND in a star shape
fashion (in order to avoid impedance coupling between ICs). But I'm afraid
that If a +5V copper pour is placed in the TOP layer the star
POWER/GND distribution topology will be lost (since the pour will bond to
the +5V traces because it is electrically the same net). Should the copper
pour respect the star topology +5V traces ?*
**
*2. Should the copper pour of the TOP layer be attached to the GND net
instead?*
**
*3. A star topology has been used for placing the GND supply traces (trying
to locate them underneath +5V traces). If a copper pour is placed in the
BOTTOM layer attached to GND, the star topology will be lost (for the same
reason as topic # 1). Acording to the theory, the returning current of all
the signal traces and power traces will try to go come back right under the
respective trace providing there is a GND return trace or plane underneath
(that is, the returning current always seeks for the **least impedance
path). If +5V (TOP layer) is distributed in a star fashioned way, the
physics would take care of the rest, right? (I mean even if the bottom layer
has a GND copper pour eating up the star topology GND traces, the "mirror
effect" would "copy" the star topology from the TOP layer to BOTTOM?).
Should the copper pour respect the star topology GND traces ? *
**
I would REALLY appreaciate if you kindly could provide some advices about
these matters.
THANK YOU SO MUCH BEFOREHAND.
--
Carlos Toro B
Design Engineer
JAVERIANA STEREO
Calle 18 No. 118-250
Cali, Colombia
South America
Office Phone: +57 2 2725032
Mobile Phone: +57 315 474 5872
Are there any bare-board vendors in Columbia
that can manufacture 4-layer boards?
Otherwise,
1) It doesn't matter if the +5v pour "bonds with"
the +5v traces
2) no
3) no. Let the GND pour fill wherever it can.
Jack
-=-=-=-
Jack. Thanks for your reply. There aren't any 4-layer boars manufacturers
in Colombia (as far as I know).
Our company attempts to evaluate if the boards can be ordered locally in
order to reduce costs.
Regarding your answers. I'm still not sure if I wanna loose my star +5V
scheme distribution... particularly,
I'm afraid that placing a copper pour attached to the +5V net would vanish
that scheme. What would you recommend
us in that case?
Thanks beforehand for your attention.
Regards,
Carlos Toro B
Design Engineer
JAVERIANA STEREO
Calle 18 No. 118-250
Cali, Colombia
South America
Office Phone: +57 2 2725032
Mobile Phone: +57 315 474 5872
Hi Carlos,
I should apologize for my reply. I was assuming that you were on the wrong
track tryin to accomplish that design with only two layers. I got a private
reply that made me understand more about what you are trying to do. I am not
experienced enough to help you, sorry.... but here is a rsponse I got. Hope
it helps...
-=-=-=-
Hi Jack,
You may catch some flack for the responses.
1. It absolutely makes a difference how the power is distributed on a
surface layer (think moats and bridges and preventing eddy currents or
power loops), especially on the component side where you don't want the
power plane directly underneath the chips as the digital switching noise
from the power plane will couple to the device making the IC a radiator,
in addition to adding the noise to the chip itself and trashing the
signals within. The ideal, without knowing the circuit, would be to
distribute the power with thick traces, surrounding these traces with
GND and flood the balance of the top layer with GND and stitch it with
vias to the bottom side GND (think a three sided co-ax cable). BP cap
placement is critical.
2. Absolutely, see item 1. With a double sided PCB, assuming .062 thick
FR-4 and a dielectric constant of 4.2, the return path coupling is
rather poor, especially at higher speeds. Using a thinner PCB will help
dramatically.
3. Depends on the circuit, again, moats and bridges. A solid, unisolated
GND plane can become an unintended coupling mechanism. In many instances
you mirror the moats with slightly larger GND (flux edge coupling) to
maintain the isolation and control current flow.
The most difficult PCBs to design correctly from a physics perspective
are double-sided.
You're safer directly responding to the post and letting them filter
through the responses unless you're looking to collect a larger response
from the list.
David Lieby <dlieby@xxxxxxxxxx> to si-list
I would like to add:
If it is possible to use jumper wires instead of routing signals to the
bottom of the board you can keep a very good ground plane. It could be
possible to just route signals that are not too impedance sensitive this
way to keep things quiet.
I would pour +5V on the top.=20
Regards,
dav0
David Lieby=20
dav0
David Lieby
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