[SI-LIST] Fw: SI engineer job opportunities at Hisilicon (huawei) in Shanghai or Shenzheng, China

  • From: yinhongcheng <yinhc@xxxxxxxxxx>
  • To: si-list <si-list@xxxxxxxxxxxxx>
  • Date: Mon, 30 Jun 2008 10:46:58 +0800

Hi All,
 
      Some  SI immediate job opportunities are still opening, you can visit our 
website(http://www.hisilicon.com/cn/ ) to get more detailed information,
Please contact Me directly if you are interested.  
Here is a general job responsibility Description:  
  1.        Evaluation and choice of 3rd party IO buffer and SerDes IP for ASIC 
design.

  2.        Definition of board level network topologies. 

  3.      Creation of interconnect models. 

  4.        Creation of Hspice circuit simulation decks. 

  5.      Simulation of these Hspice decks and output IO buffer delay, 
transition timing parameters.

  6.        Lab debug of signal integrity, noise and/or timing issues. 

  7.      Definition of the ASIC IO pad ring. 

  8.        Understanding the ASIC power sequencing requirements. 

  9.     SI guidelines for package design. 

  10.  Documentation. 

   

  Requirements: 

   

  1.        BSEE or BS Physics with above 3 year experience and MS with above 2 
year experience are required, a  PhD is preferred. 

  2.        2 years of hands-on circuit level simulation experience with 
Hspice. 

  3.        2 years of experience in signal integrity analysis. 

  4.      understanding of both the theoretical and real-world aspects of 
electromagnetic field theory, transmission lines, crosstalk, ISI, SSN, jitter 
and other signal integrity phenomena is a plus.

  5.      Experience with serial communication standards and protocols is 
required; experience with SerDes implementations and experience with the PCI 
Express and XAUI interfaces is a plus.

  6.        Experience with high-speed digital communication standards is 
required; experience with CML, LVDS, SSTL, HSTL and PCI specifications is a 
plus. 

  7.      Experience with semiconductor IO circuit design is a plus. 

  8.        Experience with package design and analysis is is a plus. 

  9.        Experience with 2D and 3D field solvers is a plus. 

  10.  Practical, hands-on experience with high-speed lab test equipment is a 
plus.

  11.  Experience in taping out multi-million gate CMOS ASICs in 130nm 
technology and below, an understanding of the IC signal integrity effects 
present in these technology nodes and familiarity with the design flows is a 
plus.








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