[SI-LIST] Re: Fw: Re: Random Jitter Value varies with Data pattern
- From: Marty Miller <martym777@xxxxxxxxx>
- To: "Alfred P. Neves" <al@xxxxxxxxxxxxxxxxx>, "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Tue, 5 Feb 2013 17:24:01 -0800 (PST)
In my humble opinion, "N-cycle" jitter is old-speak. Daniel Chow from Altera
and I published a white-paper on this in 2005.
http://cdn.teledynelecroy.com/files/whitepapers/wp_techbrief_var_of_time.pdf
This methodology was well-suited to Time Interval Analyzers (TIAs), but could
also be implemented in RT oscilloscopes. Usually when people talk about Rj, Dj
and Tj these days, it's
about "Time Interval Error" (TIE).
I'm not sure it's public, but when I want to calculate the Jitter Transfer
Function (JTF), which is a very straightforward, useful concept (and rather
removed from the description of the PLL's loop response) I use an
Excel VBS macro and the built-in Jitter Simulator to produce a graph. Some
slides from the DesignCon jitter panel the year I met you show how this JTF
depends on the data pattern.
The T&M guys who understood the importance of timebase jitter were way out in
front of this, some before others.
________________________________
From: Alfred P. Neves <al@xxxxxxxxxxxxxxxxx>
To: jory_mckinley@xxxxxxxxx; martym777@xxxxxxxxx
Sent: Tuesday, February 5, 2013 6:58 PM
Subject: Re: [SI-LIST] Re: Fw: Re: Random Jitter Value varies with Data pattern
My understanding is you plot the accumulated N-UI variance record, it should
look like PLL loop response. Specifically, plot 1UI jitter RMS, then 2UI,
then 3... and so on.
I have a bit of Wavecrest data that I used to calculate PLL peaking, loop BW,
and it worked really well. Marty, can the LeCroy real time scopes do this?
Most of my work was back in the day the real time scopes had excessive time
base jitter.
Products for the Signal Integrity Practitioner
Alfred P. Neves
Chief Technologist
Office: 503-679-2429
www.wildrivertech.com
On Feb 5, 2013, at 3:45 PM, Jory McKinley <jory_mckinley@xxxxxxxxx> wrote:
Hello Vinod/Marty,"That aside, you say you are using a "constant clock". By
this I assume you are measuring jitter of the data-stream (PRBS11) relative to
a clock. I assume it's the clock that is used to generate the PRBS11, in which
case a PLL is not needed (you don't need to recover a clock, because you
already have a clock). If this is the case, then I really don't understand why
you are seeing increased Rj for PRBS11. Can you send me a data-set (in Agilents
"bin" format, preferably). Or even just a picture of the histograms of the
jitter."
>I think you folks are missing the basic concept that RJ will tend to grow with
>the square root of your N-UI assuming the clock and data are generated from
>the same source. As you increase the time domain N-UI you effectively add
>more frequency domain sampling bins in RJ calculation. This relationship is
>roughly sqrt(N-UI) but not really since RJ is not spectrally flat and grows up
>to the close loop bandwidth of the PLL then the PLL rejects VCO phase noise
>and your end up measuring the RJ of its reference clock.
>Given an acceptable record length your DjDD should be relatively constant over
>N-UI while RJ will increase roughly as the sqrt(N-UI).
>
>-Jory
>>
>________________________________
>From: Marty Miller <martym777@xxxxxxxxx>
>To: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
>Sent: Tuesday, February 5, 2013 4:52 PM
>Subject: [SI-LIST] Fw: Re: Random Jitter Value varies with Data pattern
>
>
>
>----- Forwarded Message -----
>From: Marty Miller <martym777@xxxxxxxxx>
>To: vinod ah <ah.vinod@xxxxxxxxx>
>Sent: Tuesday, February 5, 2013 12:46 PM
>Subject: Re: [SI-LIST] Re: Random Jitter Value varies with Data pattern
>
>
>Does your DUT have SSC turned on? If so that would explain a lot.
>
>
>________________________________
>From: vinod ah <ah.vinod@xxxxxxxxx>
>To: Marty Miller <martym777@xxxxxxxxx>
>Sent: Tuesday, February 5, 2013 12:16 PM
>Subject: Re: [SI-LIST] Re: Random Jitter Value varies with Data pattern
>
>
>Forgot to mention on the bit rate, the bit rate seems to be varying little bit
>due to PLL clock tolerances which is used to generate the PRBS 11 pattern in
>DUT. I see that PLL clock used for PRBS 11 gen at DUT has both positve and
>negative PPM at different instants of time. Could this be the reason for
>accumulation of large Rj when the pattern captured increases.
>
>
>On Tue, Feb 5, 2013 at 10:35 PM, vinod ah <ah.vinod@xxxxxxxxx> wrote:
>
>I think i did not put my statement properly regarding "constant clock", sorry
>for that. Jitter software asks for clock recovery option before it measures
>jitter i.e. to specify whether we need PLL with certain bandwidth or constant
>clock.
>
>This oscilloscope internal clock is not related to clock used in DUT for
>generation of PRBS 11 pattern.
>>
>>
>>So basically the oscilloscope is using a constant clock to measure the jitter
>>in PRBS 11 pattern fed to it. Not sure what is the real meaning of constant
>>clock in Jitter software of oscilloscope. I am using Tek scope with DPOJet
>>software for Jitter analysis.
>>
>>
>>
>>
>>On Tue, Feb 5, 2013 at 9:43 PM, Marty Miller <martym777@xxxxxxxxx> wrote:
>>Well, jitter is any variation in edge timing from an "expected" edge time. If
>>no PLL is used, the expected edge times are specified by only 2 things, a
>>detected starting phase, and the frequency assumed to be the bitrate. All RT
>>oscilloscopes can adequately determine both of these, but you may or may not
>>be letting the RT scope re-calculate a "best" frequency. If the frequency is
>>wrong even by a little, the timing errors "jitter" have a cumulative error
>>that contributes. The longer the waveform that is analyzed, the more
>>cumulative error there is. Very low frequency jitter is also not "removed" by
>>the PLL, and so it also contributes to the jitter, and the longer the
>>waveform, the lower the frequencies that can contribute. With no PLL the
>>frequency that can really hurt is DC (zero Hz).
>>
>>
>>>
>>>That aside, you say you are using a "constant clock". By this I assume you
>>>are measuring jitter of the data-stream (PRBS11) relative to a clock. I
>>>assume it's the clock that is used to generate the PRBS11, in which case a
>>>PLL is not needed (you don't need to recover a clock, because you already
>>>have a clock). If this is the case, then I really don't understand why you
>>>are seeing increased Rj for PRBS11. Can you send me a data-set (in Agilents
>>>"bin" format, preferably). Or even just a picture of the histograms of the
>>>jitter.
>>>
>>>
>>>You can find my paper here:
>>>
>>>
>>>http://cdn.teledynelecroy.com/files/whitepapers/designcon2013_understanding_apparent_increasing_random_jitter_with_increasing_prbs_test_pattern_lengths.pdf
>>>
>>>
>>>
>>>
>>>________________________________
>>>From: vinod ah <ah.vinod@xxxxxxxxx>
>>>To: Marty Miller <martym777@xxxxxxxxx>
>>>Sent: Monday, February 4, 2013 10:46 PM
>>>Subject: Re: [SI-LIST] Re: Random Jitter Value varies with Data pattern
>>>
>>>
>>>
>>>Hi Miller,
>>>
>>>
>>>The DUT is generating patterns (like 2.5GHz and PRBS 11) which is connected
>>>to an oscilloscope where no PLL is used. Instead of PLL i am using constant
>>>clock for sampling to measure the jitter. Certain serial standards do
>>>mention the PLL specs for jitter measurements.
>>>
>>>
>>>Is it possible to brief the point "The behavior you describe is easily
>>>achievable by having a slight error in frequency (bit rate)". I was not able
>>>to understand the relation between varying bit rate and jitter :-)
>>>
>>>
>>>Also can you please share the paper presented if it is not confidential so
>>>that i can understand better.
>>>
>>>
>>>Regards
>>>Vinod A H
>>>
>>>
>>>On Mon, Feb 4, 2013 at 11:58 PM, Marty Miller <martym777@xxxxxxxxx> wrote:
>>>
>>>Vinod, I'd like to offer some advice, but first I would ask what
>>>Clock-Data-Recovery are you using?
>>>
>>>The behavior you describe is easily achievable by having a slight error in
>>>frequency (bit rate). For whichever
>>>>method you use repeating or arbitrary, you will get the same behavior for
>>>>such a case.
>>>>
>>>>
>>>>I presented a paper at DesignCon last week on precisely the subject of
>>>>increasing Rj with increasing PRBS
>>>>lengths. That paper concerns much longer test patterns than you are using.
>>>>
>>>>
>>>>
>>>>________________________________
>>>>From: vinod ah <ah.vinod@xxxxxxxxx>
>>>>To: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
>>>>Sent: Friday, February 1, 2013 1:16 AM
>>>>
>>>>Subject: [SI-LIST] Re: Random Jitter Value varies with Data pattern
>>>>
>>>>
>>>>Hi All,
>>>>Sorry for not mentioning few details. My mistake. Below are the same.
>>>>
>>>>Scope: Real time
>>>>BW: 12.5GHz
>>>>Sampling rate : 100Gs/s
>>>>Record length used: 1M
>>>>Time base setting: 1us/div
>>>>Signal fed: PRBS 11 and 2.5GHz clock
>>>>
>>>>Below are the few observation which i could make in last 2 days in process
>>>>of finding out dependency of Rj on data pattern.
>>>>
>>>>1) In Jitter decomposition software, when i set the Pattern type
>>>>as Arbitrary (when capturing PRBS pattern) and Window length as 2UI, i see
>>>>that the Rj value is very near to Rj value measured with clock pattern. I
>>>>understand that the technique used to separate Rj Dj is different if we set
>>>>Pattern type as Arbitrary or Repeating. Does it mean that algorithm used
>>>>for Arbitrary pattern converges to Repeating pattern algorithm when we set
>>>>the window length as 2UI?
>>>>
>>>>2) As i increase the window length for arbitrary pattern setting from 2UI
>>>>to 5UI, the Rj
>>>>vaule keeps increasing dramatically. But Dj value seems to
>
>be pretty much constant. Dj not increasing implies ISI is fully captured,
>>>>but Rj increasing not sure !!!
>>>>
>>>>3) As the number of samples considered (Record length) increases, both Rj
>>>>Dj increases. Most of measurements are taken with Record length of 1M, but
>>>>if i make it 10M with all other settings remaining same, i see that Rj and
>>>>Dj both give very high readings.
>>>>Is there any rule which says what should be the record length for certain
>>>>type of jitter measurement?
>>>>
>>>>4) I see minor difference in readings of Rj Dj when using Real time
>>>>sampling compared to Interpolated real time sampling. Is this expected?
>>>>
>>>>Regards
>>>>Vinod A H
>>>>
>>>>On Wed, Jan 30, 2013 at 4:35 AM, T.K. Jeon <tkjeon@xxxxxxxxxxx> wrote:
>>>>
>>>>
>>>>Hi Vinod,
>>>>>
>>>>>Most of jitter software use the jitter
>>>>>spectrum in order to separate RJ
>
>and PJ. In general, any spectral peak is considered as PJ and RJ would be
>>>>>obtained by averaging the rest of the power spectrum.
>>>>>
>>>>>As Steve mentioned, RJ should be independent of the pattern in the ideal
>>>>>case. However, in reality, RJ could be affected by both the pattern length
>>>>>and the data acquisition memory. Let me show you an example.
>>>>>
>>>>>Assuming that your scope has 1M of acquisition memory with 40GSa/s for
>>>>>5Gb/s signal, I get the number of samples like 1M/(40G/5G)5K. The
>>>>>samples will contain 61 times of your PRBS11 pattern (125K/(2^11-1)), while
>>>>>62500 times of your clock pattern(125K/2). You will see significant
>>>>>difference in terms of the jitter samples covering the whole data pattern.
>>>>>This difference could cause RJ discrepancy after power spectrum average.
>>>>>
>>>>>Best Regards,
>>>>>TK
>>>>>
>>>>>
>>>>>-----Original Message-----
>
>From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
>>>>>On Behalf Of vinod ah
>>>>>Sent: Monday, January 28, 2013 1:24 AM
>>>>>To: weirsi@xxxxxxxxxx
>>>>>Cc: si-list@xxxxxxxxxxxxx
>>>>>Subject: [SI-LIST] Re: Random Jitter Value varies with Data pattern
>>>>>
>>>>>DUT itself is signal generator which generates either PRBS pattern or clock
>>>>>pattern based on certain register settings. The DUT is connected to an
>>>>>oscilloscope where a jitter decomposition software runs.
>>>>>On Mon, Jan 28, 2013 at 2:15 PM, steve weir <weirsi@xxxxxxxxxx> wrote:
>>>>>
>>>>>
>>>>>Truly random jitter is independent of the data pattern. Do you see this
>>>>>>jitter going straight from a pattern generator into a signal analyzer,
>>>>>>or only when your DUT is in the path?
>>>>>>
>>>>>>Steve
>>>>>>
>>>>>>On 1/27/2013 10:57 PM, vinod ah wrote:
>>>>>>
>>>>>>Hi All,
>>>>>>>On a 5Gb/s USB3 serial link, i see that there is variation in Random
>>>>>>>jitter
>>>>>>
>>>>>>value when i use CP0 pattern (PRBS 11 pattern) when compared to CP1
>>>>>>>pattern
>>>>>>
>>>>>>(Clock pattern 2.5GHz).
>>>>>>>
>>>>>>>I also see a variation in deterministic jitter, but that is more
>>>>>>>understandable as ISI effects are dominant with PRBS pattern and it is
>>>>>>>pretty much constant with clock
>>>>>>>pattern.
>
>
>>>>>>>Is Random jitter varying with data pattern is expected?. The difference
>>>>>>>in
>>>>>>
>>>>>>readings is 2ps (Rj with PRBS is 5ps mean, while Rj with clock pattern
>>>>>>>is
>>>>>
>>>>>3ps mean)
>>>>>>>
>>>>>>>Note: The measurements are not dual-dirac model based measurements.
>>>>>>>
>>>>>>>Regards
>>>>>>>Vinod A H
>>>>>>>
>>>>>>>
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>
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>
>>>>>>--
>>>>>>Steve Weir
>>>>>>IPBLOX, LLC
>>>>>>1580 Grand Point Way
>>>>>>MS 34689
>>>>>>Reno, NV 89523-9998
>>>>>>www.ipblox.com
>>>>>>
>>>>>>(775) 299-4236 Business
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>>>>>>(707) 780-1951 Fax
>>>>>>
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