[SI-LIST] Re: Fw: Re: AW: Re: Some reference on reference planes

  • From: Lee Ritchey <leeritchey@xxxxxxxxxxxxx>
  • To: eliaissa1@xxxxxxxxx, "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
  • Date: Mon, 5 Mar 2012 10:24:57 -0800 (GMT-08:00)

Larry's points are well taken and what I have meausred in real PCBs.  Good news 
is that the onset of differential signalling has reduced the incidence of large 
parallel buses is most designs.  Life has gotten easier as a result rather than 
harder!  About the only large parallel buses I see are DDR address buses which 
should not have to cross cuts in planes.

Lee


-----Original Message-----
>From: elie issa <eliaissau1@xxxxxxxxx>
>Sent: Mar 4, 2012 11:23 AM
>To: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
>Subject: [SI-LIST] Fw: Re: AW: Re: Some reference on reference planes
>
>I think it is a proper email to share on the si list, as a contributor.
> 
>----- Forwarded Message -----
>From: elie issa <eliaissa1@xxxxxxxxx>
>To: "Smith, Larry" <larrys@xxxxxxxxxxxx> 
>Sent: Friday, November 11, 2011 11:48:52 AM
>Subject: Re: [SI-LIST] Re: AW: Re: Some reference on reference planes
>
>Larry:
>Only portion of the frequency spectrum of a fast edge crosses the split and 
>the rest could go around it, so it is never continuous
> 
>Regards
>Elie
>
>From: "Smith, Larry" <larrys@xxxxxxxxxxxx>
>To: Lee Ritchey <leeritchey@xxxxxxxxxxxxx>; Mark Grobman 
><markgrobman@xxxxxxxxx>; "Havermann, Gert" <Gert.Havermann@xxxxxxxxxxx>
>Cc: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
>Sent: Wednesday, November 9, 2011 5:28:51 PM
>Subject: [SI-LIST] Re: AW: Re: Some reference on reference planes
>
>Lee and all - You have some good comments in your response but I feel we are 
>missing some important concepts in this thread.  How many signals are going to 
>cross the plane cut on this high performance PCB?  If it is just one, the 
>consequences will be minimal.  If it is 100 - watch out!  
>
>We know what happens to the current on the 50 Ohm trace that crosses the plane 
>cut, it just goes straight across while it suffers from a small impedance 
>discontinuity.  But what happens to the return current?  The answer depends 
>upon the frequency band where we ask the question.  As several posters on this 
>thread have pointed out, a fast rise time signal will have GHz frequency 
>content and the return current in that frequency band must make its way across 
>the plane split through each power plane capacitance to (hopefully continuous) 
>ground plane somewhere in the stackup.  If the signal pulse has a long 
>duration and is parallel terminated at the far end, return current at 100's 
>and 10's of MHz will find its way through discrete ceramic and bulk decoupling 
>capacitors.  If the signal pulse lasts for a very long time, return current in 
>the kHz band down to DC will return through the voltage regulator.  
>
>When the signal edge hits the plane discontinuity, power plane bounce ripples 
>out in space with the disturbance uncovering more and more power plane 
>capacitance as time goes on.  The entire Power Distribution System gets 
>involved if the signal current is long enough in time duration.  So the 
>question we should be asking is about the impedance of the PDS measured at the 
>points on each power plane where the signal return path discontinuity occurs, 
>and we would like to know these impedances in the important frequency bands.  
>How does the PDS impedance compare to that of the 50 Ohm trace?  At DC, kHz 
>and MHz bands, the PDS will most likely be in the mOhms and it will be quite 
>strong compared to the 50 Ohm trace.  In the GHz band, the impedance of the 
>PDS will be low as long as the dielectric thickness from power to ground plane 
>is small.  But in the stackups mentioned in this thread, some of the power 
>planes are quite far from the ground plane so the
> plane capacitance and impedan
>ce suffers.  Still, the PDS is likely to be much stronger than the 50 Ohm 
>trace so power plane bounce will be minimal.
>
>But watch out if 100 traces cross the plane cut, particularly if they can 
>switch the same direction at the same time.  This potentially causes a huge 
>SSN problem.  100 traces in parallel have an equivalent impedance of 50/100 = 
>0.5 Ohms and are likely to be a challenge for the PDS impedance in the GHz 
>band.  The voltage regulator and decoupling capacitors should be able to 
>handle the return current in lower frequency bands but much crosstalk will 
>occur because of power plane bounce in the GHz band.
>
>In reality, there will probably be a number of traces that is greater than 1 
>but less than 100 crossing the plane cut so analysis will have to be done to 
>figure out the damage.  Do we care about high frequency glitches coupled from 
>aggressor to victim lines?  How important is rise time degradation and EMI?  
>These are the important considerations in this problem.
>
>Regards,
>Larry Smith
>Qualcomm
>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On 
>Behalf Of Lee Ritchey
>Sent: Tuesday, November 08, 2011 4:59 PM
>To: Mark Grobman; Havermann, Gert
>Cc: si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Re: AW: Re: Some reference on reference planes
>
>Wow!  This one has taken on a life of its own!
>
>Couple of things gleaned from building test PCBs to find out what happens 
>when traces cross cuts in planes as well as hundreds of high performance 
>PCBs.
>
>First, there is no good reason to cut a ground plane, so that should be the 
>mechanism that ties all other things together.
>
>Second, when the PDS has been properly designed, the ripple on Vdd will be 
>low enough that it is within the noise budget of signals routed over it, so 
>there is no reason not to route signals over Vdd and use it as a reference 
>plane.
>
>Third, the only planes that should ever be cut are Vdd planes to allow more 
>than one Vdd to use the same plane.  These cuts do not need to be wider than 
>10 mils to satisfy isolation and fabrication needs.  When this is done and 
>the two Vdds on either side of the cut are properly designed, there is an 
>"AC" path across the cut created by the two Vdd supplies that render the cut 
>essentially invisible to signals crossing it.  I've got several test PCBs 
>that validate this.  Some of the measurements are in one of my books and 
>others are presented in my classes.  There is no need to place capacitors 
>across these gaps.  The PDS has already done this.
>
>Now, all of this comes unraveled if the PDS design has not been done well or 
>if the ground planes have been cut.  There other things that come unraveled 
>as well, such as EMI and stable operation.
>
>This PDS design issue has become one of the hot topics of late as witnessed 
>by all the papers presented at DesignCon.  Few if any applications notes 
>provide accurate advice on how to do this right.  To this end, Todd Hubing, 
>when he was at University of Missouri Rolla,  did several tests and analyses 
>and published the results as far back ad 1995.  His specialty was EMI, but 
>he knew that the source of much EMI was an improperly designed PDS arrived 
>at by following applications notes. Yet, applications notes still don't 
>incorporate these findings.
>
>Hope this helps.
>
>Lee
>
>--------------------------------------------------
>From: "Mark Grobman" <markgrobman@xxxxxxxxx>
>Sent: Tuesday, November 08, 2011 1:21 PM
>To: "Havermann, Gert" <Gert.Havermann@xxxxxxxxxxx>
>Cc: <si-list@xxxxxxxxxxxxx>
>Subject: [SI-LIST] Re: AW: Re: Some reference on reference planes
>
>> Ok, at the risk of being naive, I would like to try to put in some 
>> numbers:
>> Most of my signals have a 0.5ns rise time. assuming a dielectric constant
>> of 4 that would mean signal velocity of 2Exp10 Cm/Sec (sorry for using
>> metric units). I assume that the highest relevant harmonic is at ~ 10GHz 
>> so
>> my wavelength is about ~2cm.
>> Now we come to the tricky part of trying to evaluate how long is the
>> discontinuity - since the currents return to the rightful owner near the
>> BGA package and the pitch is 0.8mm than we roughly ar the vicinity of the
>> 1/4 wavelength.
>> According to this calculation the situation isn't brilliant but it's also
>> not apocalyptic - I mean the edges might smooth out a bit but on the whole
>> the signal will be ok.
>>
>> Then there is the question of crosstalk - I don't know how bad that would
>> be but the suggestion that Paul gave about adding decoupling caps between
>> the real ref planes and the ones the signal uses seems to help the
>> situation.
>>
>> I could add that we have a previous board with slightly slower freq. that
>> ha×' a similar stackup and it works fine on all accounts.
>> I would also stress that this is not a matter of economy of layers\money -
>> the small aspect ratio of via's caused by board thickness is a real 
>> problem
>> and causes boards to fail.
>>
>> any more ideas? Doesn't this problem exist in other places where there
>> exist a constraint of board thickness and the necessity for many signal 
>> and
>> different power layers?
>>
>> Thanks again for all the replys'
>> Mark
>>
>>
>>
>>
>> On Tue, Nov 8, 2011 at 11:21 AM, Havermann, Gert 
>> <Gert.Havermann@xxxxxxxxxxx
>>> wrote:
>>
>>> Hi Mark,
>>>
>>> With the chosen stack and without the ability to simulate 3D you are
>>> pretty screwed. You absolutely have to provide a clean GND return path.
>>> This is easy with ref-planes directly attached, but without it is (in 99%
>>> of the cases) too complicated to do "by hand". There are no proven rules 
>>> of
>>> thumb or design practice for these odd designs.
>>>
>>> The only thing (besides adding Layers) you could do is to think yourself
>>> into the signal path to find out:
>>> - what are the reference planes for the signal?
>>> - what differential and single ended impedance will the wave see based on
>>> the reference planes?
>>> - where is the shortest possible GND path along the electric field of the
>>> signal?
>>> - what is the electrical and length difference between signal and GND 
>>> path?
>>>
>>> With a lot of thinking and calculation, you might be able to get an 
>>> answer
>>> to your problem, but if there are many signals involved I doubt you can
>>> make it (Murphy will play against you).
>>>
>>> Regarding you questions:
>>> The risetime isn't setting the limit, it's the GND-return discontinuity.
>>> The shorter the discontinuity, the lower the risetime can be. If the
>>> electrical length difference between the signal trace and GND retun path
>>> exceeds 1/4 wavelength, you will be in trouble.
>>>
>>> I the worst case, you will have to worry about interferences all across
>>> the board. E.g. if return currents are forced to cross thru ICs, you will
>>> face strange behavior of a component while it's the PCB that's making the
>>> error. You also open the door for all kind of EMC problems that you might
>>> not find in the Lab, but they will hit you in the field.
>>>
>>> Good Luck
>>> Gert
>>>
>>>
>>>
>>> --------------------------------------------------------------------------
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>>> -----Ursprüngliche Nachricht-----
>>>
>>> Von: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
>>> Im Auftrag von Mark Grobman
>>> Gesendet: Dienstag, 8. November 2011 05:46
>>> An: Jory McKinley
>>> Cc: Rick Collins; si-list@xxxxxxxxxxxxx
>>> Betreff: [SI-LIST] Re: Some reference on reference planes
>>>
>>> Hey all,
>>> I'm sorry - it seems I've confused all you (perhaps this is a reflaction
>>> of my own confusion).
>>> my stackup is 18 layers and is perfectly symmetrical. The stackup I wrote
>>> down is a "zoom" on the problematic area just so you could understand 
>>> where
>>> my problem is.
>>>
>>> As for the combining of power planes: As I stated - the situation cannot
>>> be avoided without increasing the number of layers ( i tried combining 
>>> but
>>> it doesn't work) which I am reluctant to do due to reliablity issues 
>>> caused
>>> by the via's aspect ratio.
>>>
>>> What I really want to understand is: If I was making a DC board than we
>>> wouldn't be having this discussion. Since this is a digital board life
>>> isn't so simple (don't tell any DC engineers I implied their job was 
>>> easy)
>>> - what is the area of rise times where problems start surfacing?
>>> Can I help mitage this issue *without *changing the stackup?
>>> And should I worry about interfernces throughout the transmission line or
>>> just near the edges/where the via's are?
>>>
>>> Thanks again for all the help,
>>> Mark
>>>
>>>
>>> On Tue, Nov 8, 2011 at 3:17 AM, Jory McKinley <jory_mckinley@xxxxxxxxx
>>> >wrote:
>>>
>>> > Hello Mark,
>>> > Assuming you have meaningful energy on this trace, I would highly
>>> > recommend modifying your stack which seems to be unbalanced without
>>> > appropriate ground planes.  The single ground plane at the bottom of
>>> > your stack is not recommended and could create all sorts of unwanted
>>> > resonances as your return current jumps to the bottom through power
>>> > cavities.  I would look to pair your power planes and combine on two
>>> > of the layers not four as you have.  I would either add another layer
>>> > and sandwich 3 grounds OR remove a layer and have the other layer
>>> > another ground.  I do not like power on top or bottom due to potential
>>> radiation.  Something like:
>>> >
>>> > TOP/LowSpeed Signal 3
>>> > Power 1(Real Ref.)/Power2
>>> > GND
>>> > Signal 1
>>> > Signal 2
>>> > GND
>>> > Power 3/Power4
>>> > BOTTOM/LowSpeed Signal 3
>>> >
>>> > The potential issues you face with improper return path can create
>>> > signal integrity and timing issues on your path and potential
>>> > resonances through the power cavities. You will not only have to
>>> > decouple near the TX and RX of the path from reference to ground but
>>> > also decouple very close to the via transitions of your trace.
>>> >
>>> > -Jory
>>> >
>>> >
>>> >
>>> > ------------------------------
>>> > *From:* Mark Grobman <markgrobman@xxxxxxxxx>
>>> > *To:* Rick Collins <gnuarm.2006@xxxxxxxxx>
>>> > *Cc:* si-list@xxxxxxxxxxxxx
>>> > *Sent:* Monday, November 7, 2011 4:40 PM
>>> >
>>> > *Subject:* [SI-LIST] Re: Some reference on reference planes
>>> >
>>> > Thanks for the quick reply's.
>>> > Paul - I read in Bogatain's book that this method is not effective -It
>>> > was mentioned under what happens when you run over a gap in the return
>>> > plane but as I understand the physics is essentilay the same. To the
>>> > best of my understanding the current will "find it's way back" in a
>>> > radiative manner so that as long as the capacitance between the
>>> > relevent planes is suffiecnt it should be ok above a certain rise 
>>> > time -
>>> I just don't know the numbers.
>>> > Is this method effective from your experince? what's the range of Rt
>>> > for which it works.
>>> >
>>> > Rick - Your absoulty right. I've been a bit vauge. The setup I'm
>>> > talking
>>> > > about is something like this:
>>> > >
>>> > Power 1(Real Ref.)
>>> > Signal 1
>>> > Power 2
>>> > Signal 2
>>> > Power 3
>>> > Signal 3
>>> > Power 4(GND)
>>> >
>>> > And the relevent Signal layer is "Signal 2". The distance between
>>> > different layers is 5 mil on each side.
>>> >
>>> > Mark
>>> >
>>> > >
>>> > On Mon, Nov 7, 2011 at 11:24 PM, Rick Collins <gnuarm.2006@xxxxxxxxx>
>>> > wrote:
>>> >
>>> > > I recall from a course I took that if the plane of the stripline is
>>> > > tightly coupled to the reference plane, you should not have a
>>> > > problem.  But "tightly coupled" may not be what you have.  I think
>>> > > the context of what I learned was when there was a separation in a
>>> > > power plane or even a signal passing across a gap between two
>>> > > separate power planes, but in both cases the power planes were
>>> > > opposite a ground plane and so were "tightly coupled" acting just
>>> > > like the ground plane.
>>> > >
>>> > > Where is your driver's "reference plane" that it does not interact
>>> > > with the signal?  Can you give us a better picture of what you are
>>> > > designing rather than talking in the abstract?
>>> > >
>>> > >
>>> > > At 04:15 PM 11/7/2011, Mark Grobman wrote:
>>> > > >Hello experts,
>>> > > >I require some help on the subject of reference planes. I'm
>>> > > >designing a board and despite my best efforts i'm stuck with a
>>> > > >situation where I'm forced to conduct a signal using a stripline
>>> > > >neither of whose planes are the reference planes of the signal's
>>> > > >driver (not the driver's ground or VCC).
>>> > > >
>>> > > >Now I know from various App. notes and books that this sort of
>>> > > >situation should be avoided and that I have been a bad engineer
>>> indeed.
>>> > > >
>>> > > >Still, assuming the situation cannot be avoided  I was hoping to
>>> > > >get some quantitative approximation to how bad of an idea this
>>> > > >is.Sadly speaking I don't have access to a 3d simulator which can
>>> > > >give me exact results so I'm going for best effort design methods.
>>> > > >I would love to get your input on the following issues:
>>> > > >
>>> > > >1. Does the interference caused by not using the correct ref.
>>> > > >planes
>>> > carry
>>> > > >throughout the transmission line or does it occur only at the edges
>>> > where
>>> > > >the current "jumps" back to the correct ref. planes?
>>> > > >2. Is there a merit figure of RiseTime/planes capacitance/????  for
>>> > which
>>> > > >the situation isn't problematic?
>>> > > >3. Will using diff. lines improve the situation?
>>> > > >4. Suggested reading on the matter.
>>> > > >5. Highly insightful remarks which will blow my mind.
>>> > > >
>>> > > >Cheers,
>>> > > >Mark
>>> > > >
>>> > > >
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I just used the energy it took to get mad and wrote some blues.  Count Basie

Lee W. Ritchey
Speeding Edge
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