[SI-LIST] Re: Fw: AC or DC Coupling Selection

  • From: "Chen, Sherman" <sherman.chen@xxxxxxx>
  • To: "weirsi@xxxxxxxxxx" <weirsi@xxxxxxxxxx>, "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
  • Date: Sun, 9 Nov 2014 04:15:04 +0000

As I know only SATA allows DC coupling and I wonder why PCIe, SAS and other 
serdes don’t allow so (correct me if DC coupling is actually in the standard). 
Is this bcs normally an AC common voltage produced by the chip can easily go 
above the 150mV limit for AC coupling? 
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On 
Behalf Of steve weir
Sent: Sunday, October 26, 2014 8:12 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Fw: AC or DC Coupling Selection

If you DC couple then you need to look at the CMR of the receiver, the CMV of 
the transmitter, and the amount of CM noise that can exist between the two in 
your application.  CM differences are common between FPGA SERDES that seek to 
accommodate many signaling standards and ASICs / ASSPs built to a particular 
standard.  AC coupling is common practice with FPGA SERDES.  Coupling 
capacitors reject CM differences between the Tx and Rx that occur below the 
cut-off frequency.  OOB signaling in some standards have stuck us unpleasant 
side-effects of low cut-off frequencies and large coupling capacitors.  They 
also do less than nice things for TIE in the timing recovery.

Steve.

On 10/25/2014 11:55 AM, Ajay Dhingra wrote:
>
>
> -------- Original Message --------
> Subject: Re: [SI-LIST] AC or DC Coupling Selection
> From: Ajay Dhingra <ajay.dhingra@xxxxxxxxx>
> To: Orin Laney <olaney@xxxxxxxxx>
> CC: si-list@xxxxxxxxxxxx
>
> The data rates are around 6Ghz and 8b/10b is also there.
> I mainly want to understand how Vcm difference has impact specially in DC 
> Coupled interface and what are potential reasons of Vcm differences.
>
> What kind of implementations in Rx helps mitigate the Vcm difference problem.
>
> Ajay
>
> Sent from my Huawei 
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