[SI-LIST] Free webinar from Mentor Graphics HyperLynx - Part 2 of SERDES Design Solutions: Case Studies
- From: "McKinney, Steven" <Steven_McKinney@xxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Wed, 16 Sep 2009 13:52:47 -0600
Hi,
Tomorrow, Sept 17th, Mentor is hosting a webinar that will look at 2
different issues that are common to multi-Gigabit SERDES design - length
matching in differential routing and backdrilling of via stubs.
You can register for the event at the following location:
http://www.mentor.com/products/pcb-system-design/events/serdes-design-so
lutions-webseminar
Shortened link: http://tinyurl.com/hyperlynx-case-studies
You can find out more about the webinar below:
**What You Will Learn**
-- How to efficiently characterize the electrical performance of
multi-Gbps channels in the frequency and time domains
-- How to apply solution space analysis to make cost/performance
trade-offs
-- How to quantify the channel performance penalties incurred by
introducing small asymmetries in its layout
**Overview**
This session will walk you through two high speed serial channel case
studies that will demonstrate how analysis in HyperLynx provides the
essential knowledge of how a channel's physical characteristics affect
its electrical performance. This knowledge empowers the designer to make
appropriate design trade-offs. Appropriate trade-offs provide the
opportunity to shorten the design cycle, reduce manufacturing cost while
still providing conservative safety margins.
The first case study demonstrates how to quantify the performance
degradation caused by replacing blind and buried or back-drilled vias
with through-hole vias. Following these steps, the design engineer can
make an informed decision whether they can omit the expense of
back-drilling for their channel design.
The second case study demonstrates how to quantify the effect of length
miss-matches in the individual traces that make up the differential high
speed serial channel. Following these steps, the design engineer can
work with the layout engineer to decide if small deviations from trace
length matching constraints are acceptable for their design.
Best Regards,
______________
Steve McKinney
Business Development Manager
Board System Division - Analysis Products
Steven_McKinney@xxxxxxxxxx
512-425-3030
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