[SI-LIST] Free SI training in Beijing China by IO Methodology on Sept. 10

  • From: "Zhang Xinjun" <xjzhang@xxxxxxxxxx>
  • To: <si-list@xxxxxxxxxxxxx>
  • Date: Fri, 24 Aug 2007 13:26:02 +0800

This is a free training information email, please just ignore this unless
you feel it useful. Thanks.
 

 

Dear folks,

 

The IO Methodology Inc (Shanghai Likai Methodology Inc) is holding a free SI
training in Beijing, China, on Monday, September 10. The training is
sponsored by Signal Integrity Software Corp. (SiSoft) USA.

 

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

               Free SI Training  (Beijing, C H I N A )

 

Time/Date:  

Monday, September 10, 2007, 8:00 AM to 4:30 PM Meeting starts at 9:00 AM

 

Location:    

±±¾©¼¯³Éµç·Éè¼ÆÔ°, º£µíÇøÖª´ºÂ·27ºÅÁ¿×Óо×ù 4Â¥ 406--407

27 Zhichun Road

Haidian District

Beijing 100083

CHINA

           

Purpose:    

Free SI training for SI engineers, PCB layout engineers, High-Speed Circuit
Designers to bring up Chinese SI works to higher levels.

 

Provided by Shanghai Likai Methodology Co., Ltd.

Sponsored by: Signal Integrity Software Corp. (SiSoft) USA.

 

Presenters:

Lance Wang, President/CEO, IO Methodology Inc, Todd Westerhoff, VP, Software
Products, SiSoft Bob Ross, Teraspeed Consulting Group LLC,

Xinjun Zhang, Sr. SI Engineer, Shanghai Likai Methodology Co., Ltd.

Benny Yan, Sr. SI Engineer, Shanghai Likai Methodology Co., Ltd.

 

Attendant Method:

A. Call 86-21-34293088*8045 Mr. Zhu

B. Please click below link for free registration

http://www.iometh.com.cn/training/

http://www.shlikai.com.cn/training/

C. E-mail£ºsupport@xxxxxxxxxx

 

Free lunch will be provided.

 

Training Outlines

Part I SI Basic

1. Introduction to SI

2. Signal Quality

2.1 Overshoot, Undershoot

2.2 Ring back

2.3 Monotonicity

2.4 Other Signal Quality Metrics

3. Transmission Line behavior

4. Reflections

5. Xtalks

6. ISI

7. Termination Methodology

8. Topologies

Part II Serial Link

1. Digital Signal and its Frequency Bandwidth

2. Differential Pair Technology

3. Pre-emphasis Technology

4. Encoding Technology in Serial Link

Part III Parallel Link

1. Introduction

2. Pre-layout simulation

2.1 Synchronous bus (Common clock)

2.2 Source synchronous bus (DDR/DDR2/DDR3)

3. Post-layout simulation

Part IV IBIS

1. Introduction

2.1 History

2.2 Behavioral Model vs. spice model

2.3 Structure

2. I-V table

3. C_comp

4. Ramp and V-T table

5. Using IBIS in simulation

6. IBIS quality

7. IBIS extension

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

 

A confirmation Email will send shortly to the people who successfully
enrolled in this event. Please mark your calendar and see you in Beijing!

 

Thanks and Best Regards,

 

Xinjun Zhang

Consulting Engineer

IO Methodology Inc. (Shanghai Likai)

Email:  <mailto:xjzhang@xxxxxxxxxx> xjzhang@xxxxxxxxxx

 


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