[SI-LIST] Re: Fibre channel interconnect margins

  • From: "Chris Cheng" <Chris.Cheng@xxxxxxxxxxxx>
  • Date: Sat, 1 Jul 2006 12:25:47 -0700

My apology to Chris and Alan. My math is horrible. At 2+Gb/s, a BERT of 10e-12 
is hardly a matter of days but hours or even minutes. With a typical dual loop 
JBOD with a few hundred disks, we are talking about something you can see VERY 
often. Are you still saying you are shipping product like that ?
________________________________

From: si-list-bounce@xxxxxxxxxxxxx on behalf of Chris Cheng
Sent: Sat 7/1/2006 12:01 AM
To: Alan.Hiltonnickel@xxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Fibre channel interconnect margins



I know exactly what those expected and acceptable level you are talking about. 
And I have adjust and monitor them at both production and prototype level. It 
is either humping along or fall on its face and nothing in between. If you tell 
me you have indeed log those errors and get 10e-12 BERT my hats off to you. I 
have been puzzled by this 10e-xx claims for a long time and indeed very 
interested in what others do.
________________________________

From: Alan.Hiltonnickel@xxxxxxx [mailto:Alan.Hiltonnickel@xxxxxxx]
Sent: Fri 6/30/2006 10:57 PM
To: Chris Cheng
Cc: si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] Re: Fibre channel interconnect margins

You might want to re-check that. Yes, we have the same CRC checks and flags. 
But after error rates get to the "expected" or "acceptable" levels, most folks 
turn off the error reporting and let the software and hardware do what it's 
designed to do, because the system is tolerant of errors. That's the purpose of 
CRCs - to make systems more robust, not to make the customers help you debug 
your systems.

Otherwise, it sounds like you're telling us that you have invented a way to 
design equipment where randomness does not happen. Hope you got a patent on 
that! ;-)

Alan




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