[SI-LIST] Re: Fibre channel interconnect margins

  • From: Hal Murray <hmurray@xxxxxxxxxxxxxxx>
  • To: steve weir <weirsi@xxxxxxxxxx>
  • Date: Tue, 04 Jul 2006 17:41:31 -0700

> Hal, the Gaussian model really does apply and eventually your CPU
> does make mistakes.  It tends to happen at such a low rate we all
> blame it on the software or input devices that make mistakes millions
> of times more frequently.  When it comes to CPUs I am not even sure
> where to begin sifting transistor switching errors from other sources
> because the event frequency is so low. 

I believe it will happen if I wait long enough, but I don't have a good feel 
for the numbers.

I expect that I would have to wait something like the age-of-universe rather 
than just a short time like several/many years which is the time scale for 
most error mechanisms.  (at least in a well designed system)

What's the SNR for a normal CMOS signal?  (either on chip or between chips)

I'm only interested in the Gaussian part of the noise.

Where does real-life Gaussian noise come from?  Thermal/Johnson?  If so, is 
the R the output resistance of the driving transistor?  What's a typical 

What's the (Gaussian) SNR on a Fibre Channel link?  (copper and fiber)

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