[SI-LIST] Re: Fibre channel interconnect margins

  • From: "Mcgrath, Christopher" <christopher.mcgrath@xxxxxxxxx>
  • To: <si-list@xxxxxxxxxxxxx>
  • Date: Fri, 30 Jun 2006 13:03:35 -0700

Some stuff that I have done in the past to stress test FC links:
1. Max out the cable length defined by the FC-PI spec.
2. Put the product under test into a thermal chamber while varying all
voltages associated with the FC link (ASIC, SERDES, PHY, etc.) across
all corners.  (i.e. 2 voltages across hot/cold corners =3D 8 test cases)
3. User random data and not just the idle characters on the link.

Using the BER as the benchmark for acceptance (something like 10e-12),
these three things were the things we did to beat the hell out of links
before officially qualifying the physical link.

Our philosophy was to not use things like pre-emphasis or techniques
like that to stress the link but to tune the link for optimal
performance and reliability (best BER).  Once we established that after
our standard tests (#1-3 in my list) was sufficient to pass
interoperability standards with good margin (>2 orders of magnitude of
BER), we elected not to mess around with emphasis or amplitude.  The
only thing that we had to tune was the RX termination in the ASIC to
best match the board trace impedance, but this tuning was a separate
effort.

In summary:
1. Tune the link for optimal eye under lab conditions with random data
patterns.
2. Max out the cable length while testing all thermal and voltage
corners with random data patterns.

If you meet your BER requirement across several platforms, ship it!  If
not, you may have to tune the eye based on the failing corner cases.

Oh yeah- and if you are using pluggable optics then repeat the
qualification for all pluggable optic model numbers that you are
intending to ship with the unit (or put on your interoperability table)
as well. =20

-Chris




>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx] On
>Behalf Of Babid A
>Sent: Friday, June 30, 2006 11:20 AM
>To: si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Fibre channel interconnect margins
>
>Hello,
>
>  we have a fibre channal interfaces(@2.125Gbps) running on our boards
and
>looking for ways to stress the links. Right now, I am playing with
chip
>settings like pre-emphasis, equalization,amplitude, longer cables  etc.
>
>  I really apprecaite any other suggestions/ideas to stress the links
to
>find out the margins. What is the right way of quantifying the signal
>margins?
>
>  -Thanks,
>
>
>
>
>---------------------------------
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