[SI-LIST] Re: Ferrite Beads

  • From: Sammy Hindi <sammy.a.hindi@xxxxxxxxx>
  • To: aleilee2008@xxxxxxxxxxx
  • Date: Fri, 4 Dec 2015 19:27:48 -0800

Hello Tim,
Ferrite Beads are typically used for EMI suppression.
In this case a FB is added in series to VDD supply line of a clock
oscillator or a clock buffer.
FB will resonate like a tank circuit, for example the 0603 FB may resonate
between 100-400 MHz.
Under resonance condition the impedance (and Q factor) of FB will be high
to supress the HF signals or harmonics.

Using FB in series on a clock output line for edge-rate-control is not
recommended.
A simple low pass filter will do the work. A shunt cap will act with output
impedance of the driver as a simple R-C filter.

I agree with you, FB is not good to use as part of PDS circuitry.


Regards,
Sammy

On Fri, Dec 4, 2015 at 5:53 PM, aleilee2008 <aleilee2008@xxxxxxxxxxx> wrote:

usually a serial resistor or a shunt capacitor is better in the case you
discribed. FB must be deployed carefully. it may cause resonance in low
frequency. the precondition for the above is the signal line is not acting
as transmission line.

As for the harmonics of MCU inside, usually MCU manufacture will make
control to a certain level. but for the board level design, it is not a
redundant to make dwsign to suppress hamonics according to requirment



br
lei
在 2015年12月4日 下午12:11,Tim Smith <tgsmith81@xxxxxxxxx>写道:
Hi all,
Now that I have your attention with the subject title, I would like to seek
your advice on an application of ferrite beads that I have not seen covered
much in either the literature or this list.

I understand that the use of ferrite beads in the PDS without consideration
to the problem (if any) that they are trying to solve is not good
engineering. I have read through much of the discussion of their (mis)use
in PDS, but I have recently started a position in a company that uses them
in multiple applications. One being in the PDS, but I will challenge them
on this.

The other is the use of ferrite beads in the clock lines of crystal
oscillators or clock ICs. I have inquired as to their purpose and was told
that they are there to "slow" the edges of the clock down, or reduce the
magnitude of higher order harmonics.

Consider the case where a 12.0 MHz oscillator is used as the primary clock
source of an MCU that then uses a PLL to increase the core clock rate to
168.0 MHz. The 12.0 MHz clock source has higher order harmonics in the
range of 200.0 MHz which are presumably reduced by the use of the bead.
What is the resulting edge rate at the MCU pins? I haven't yet looked at
the IBIS model for the processor, but I imagine that the harmonics on the
output of the PLL would exceed 168.0 MHz thereby rendering the bead in the
clock line redundant.

My question is if the beads are helping or are redundant?
Your thoughts are appreciated.


Regards,

Dr. Timothy Smith (Ph.D)


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