[SI-LIST] Re: Fan-out in TTL and CMOS
- From: kfrobinson@xxxxxxxxxx
- To: <leeritchey@xxxxxxxxxxxxx>, <venubabu@xxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Fri, 4 Feb 2005 16:21:42 -0700
Lee,
I certainly hope you don't take yourself too seriously. ECL is dead? I
guess all the people around the world whom design ATE equipment should
just find another line of work. Maybe write books?
Ken Robinson
Micron Technology=20
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Lee Ritchey
Sent: Friday, February 04, 2005 10:10 AM
To: Ummalaneni, Venu Babu (Venu); si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Fan-out in TTL and CMOS
Venu,
Fanout is a DC loading concept for TTL. It has no meaning when talking
about high speed circuits. Driver output impedance and rise time are
what are important for COMS. CMOS inputs are purely capacitive, so they
represent no DC load. TTL is dead as a technology, so worrying about
fanout is behind us. By the way, ECL is dead as well.
Lee W. Ritchey
Speeding Edge
P. O. Box 2194
Glen Ellen, CA 95442
Phone- 707-568-3983
FAX- 707-568-3504
I just used the energy it took to be angry to write some blues.
Count Basie
> [Original Message]
> From: Ummalaneni, Venu Babu (Venu) <venubabu@xxxxxxxxx>
> To: <si-list@xxxxxxxxxxxxx>
> Date: 2/3/2005 10:11:18 PM
> Subject: [SI-LIST] Fan-out in TTL and CMOS
>
> Hi Experts,
>
> I know that fan-out in TTL circuits is decided by noise margin, i.e.;=20
> if we want more fan-out noise margin has to diminishes.
>
> In case of CMOS which factor decides the fan-out. As there is no=20
> static current drawn by the load, I hope time delay will decide the=20
> fan-out in case of CMOS.
>
> Please clear me if I am wrong. Any inputs are welcome.
>
>
> Thanks in advance
>
> Best Regards,
> Venu.
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