[SI-LIST] FWD: Re: Re: SPECCTRAQuest: DC level shift with series caps

  • From: Hassan Ali <hassan@xxxxxxxx>
  • To: si-list@xxxxxxxxxxxxx
  • Date: Thu, 14 Mar 2002 14:00:11 -0500 (EST)


On Mar 14, Bill.Cohen@xxxxxxxxxxxxxxxx wrote:

> 
> I don't know if my experience from Spice transfers to SpecctraQuest but I
> was simulating differential LVDS to PECL translators with blocking
> capacitors. I tried initializing the far end nodes to the common mode
> voltage but this was not correct. The average voltage needs to be set to
> the common mode voltage. If the initial voltage is set to VCM then the
> first transition will force the + side to (VCM + Vswing) and the - side to
> (VCM - Vswing). It took the time constant of the RC decoupling network to
> make the +voltage at the FE (VCM + 1/2*Vswing) and the - voltage (VCM -
> 1/2*Vswing).
> 
> Thus when I initialized my + and - terminals to VCM + 1/2*Vswing and VCM -
> 1/2*Vswing I could get a "correct:" looking waveform without using hundreds
> of initialization cycles. This was useful when trying out different
> networks and transceivers.
> 
> --------------------------------------------------------------
> | Bill Cohen
> | Toshiba America Electronic Components, Circuit Design Group
> | email: wcohen@xxxxxxxx
> | office: (508) 486-1031               fax: (508) 481-8828
> --------------------------------------------------------------
> 
> 
>                                                                               
>                                          
>                     Hassan
Ali                                                                             
            
>                     <hassan@xxxxxxxx>        To:     Alan Hilton-Nickel
<ahilton@xxxxxxxxxxxxx>                        
>                     Sent by:                 cc:    
si-list@xxxxxxxxxxxxx                                             
>                     si-list-bounce@fre       Subject:     [SI-LIST] Re: 
> SPECCTRAQuest:
DC level shift with series caps 
>                    
elists.org                                                                      
                   
>                                                                               
>                                          
>                                                                               
>                                          
>                     03/14/02 01:28
PM                                                                              
    
>                     Please respond
to                                                                              
    
>                    
hassan                                                                          
                   
>                                                                               
>                                          
>                                                                               
>                                          
> 
> 
> 
> 
> 
> 
> Alan,
> 
> I did try to initialize the DC level to the common-mode voltage value using
> a large
> resistor connected to a DC voltage source, but that didn't work. Looking at
> it now, I know
> why it didn't work. The setup was as follows:
> 
> 
>     Driver <--- DC_bloc_cap -----+-----> 50ohm load to gnd
>                                 <
>                                  >
>                                 <    1megaohm
>                                  >
>                                  |
>                                 ---  Common-mode voltage (DC)
> 
> The effect required is to charge the cap quickly, and the setup above
> doesn't do it as
> expected. Even if I put the 1megaohm resistor before the cap, the cap won't
> charge quickly
> owing to the very high time constant (RC) introduced by the large resistor.
> 
> As to the DC level of the output, yes, it is not absolutely zero, but
> certainly the DC
> block cap has to substantially remove the DC content of the driver output.
> 
> Bob, my link speed is 5Gbps and the 20%-80% risetime is about 20ps. You
> remember I asked a
> few days ago about broandband AC-coupling cap vendors. There doesn't seem
> to be many of
> them out there with the appropriate frequency characteristics. The passband
> is the
> problem.
> 
> Regards.
> 
> Hassan.
> 
> 
> 
> On Mar 14, Alan Hilton-Nickel <ahilton@xxxxxxxxxxxxx> wrote:
> >
> > Hassan,
> >
> > I wondered if that might be the thing to do. It's also possible in
> simulation
> > (and indeed, frequent practice), to add the resistor I suggested to set a
> DC
> > level. In simulation it would be a very large value, such as 1 to 10Meg.
> It
> > should do the trick in at most a couple of cycles. This is another way of
> > implementing Kumar's suggestion of setting the initial charge condition
> on the
> > cap.
> >
> > Also note that this effect is not necessarily a "simulation thing" -
> there is
> > some relationship to reality. If you have a cyclical signal, like a
> clock, you
> > should indeed get a 0 V DC level. But if it is data, a long string of
> "1"s or
> > "0"s will shift the DC level up or down. Even with a clock, a duty cycle
> that is
> > not exactly 50% can have a small offset. Try a 45% duty cycle in your
> simulation
> > and you'll see what I mean!
> >
> > Alan Hilton-Nickel
> > Transmeta Corp.
> >
> > Hassan Ali wrote:
> > >
> > > Thanks all for your suggestions.
> > >
> > > Actually, the sure way is that suggested by Lou - to run the simulation
> to death!
> > > Actually, in my case I had to run it for 2500 cycles!
> > >
> > > Kumar's trick is interesting. I tried it but it didn't really solve the
> problem. I
> still
> > > had to run the simulation for a long time to obtain 0V DC. I appended
> the "gsw 1 2 .."
> > > line (only one line) in the ESpice model of the capacitor.
> > >
> > > Thanks again all for the support.
> > >
> > > Regards.
> > >
> > > Hassan.
> > >
> > > On Mar 13, "C. Kumar" <kumarchi@xxxxxxxxx> wrote:
> > > >
> > > >  try this.
> > > >
> > > > cdc 1 2 my_dccap
> > > > gsw 1 2 i='if (time <= 0) (1e3 * v(1,2)) else 0'
> > > >
> > > >   Patrick_Carrier@xxxxxxxx wrote:
> > > > I agree with Lou. I know in Spice you can get around that anomaly by
> > > > specifying an initial charge condition on the cap. I don't think
> there is a
> > > > way to do that in Specctraquest though, so you need to just wait
> several
> > > > cycles to look at the waveform.
> > > >
> > > > --Pat
> > > >
> > > > -----Original Message-----
> > > > From: Sanchez, Louis [mailto:louis.sanchez@xxxxxxxxx]
> > > > Sent: Wednesday, March 13, 2002 10:55 AM
> > > > To: 'hassan@xxxxxxxx'; si-list@xxxxxxxxxxxxx
> > > > Subject: [SI-LIST] Re: SPECCTRAQuest: DC level shift with series caps
> > > >
> > > >
> > > >
> > > > Hello Hassan............
> > > >
> > > > It will take several pulses before you see the expected results in an
> AC
> > > > coupled network. I believe that you are dealing with the initial
> condition
> > > > of time it takes for all storage elements (capacitors) to reach
> equilibrium.
> > > > I suggest that you lengthen the period of your analysis in the
> Preferences
> > > > section of SigXplorer.
> > > >
> > > > Lou A. Sanchez
> > > >
> > > > -----Original Message-----
> > > > From: Hassan O. Ali [mailto:hassan@xxxxxxxx]
> > > > Sent: Wednesday, March 13, 2002 6:49 AM
> > > > To: si-list@xxxxxxxxxxxxx
> > > > Subject: [SI-LIST] SPECCTRAQuest: DC level shift with series caps
> > > >
> > > >
> > > >
> > > > Hi All,
> > > >
> > > > I'm trying to use SigXplorer to simulate a link with a differential
> > > > driver and series DC-blocking caps. Contrary to expectations,
> > > > single-ended P and N outputs measured at the load are not centered
> > > > around 0V DC, instead each one is given a separate DC shift. When I
> > > > remove the series caps, the output is as expected - centered around
> 0V
> > > > DC.
> > > >
> > > > Does anybody know what I can do to have the correct single-ended
> outputs
> > > > with the series caps?
> > > >
> > > > Thanks.
> > > >
> > > > Hassan.
> > > > ------------------------------------------------------------------
> 
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> 
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> 
> 


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