[SI-LIST] FW: TRST signal of JTAG I/F
- From: "Nico Fleurinck" <nico.fleurinck@xxxxxxxxxxxx>
- To: "'compactPCI (E-mail)'" <pci-sig@xxxxxxxx>,"'si-list'" <si-list@xxxxxxxxxxxxx>
- Date: Fri, 11 Apr 2003 08:37:15 +0200
RE: TRST signal of JTAG I/F
Hello CJ,
Many thanks for your answer!
The context is: I'm designing a compact-PCI system board with an ethernet
controller on it.
The ethernet controller is the only device on the board the has a TRST input
pin, all other devices NOT.
Because of the CPCI backplane I don't have a TRST signal that can drive the
TRST input of the ethernet controller.
What I shall do is connect the TRST input pin with the POR circuit together
with a pull-up resistor to VCC.
I don't like a passive pull-down because it will consume power and this is
not really necessary.
Sounds this OK to you?
Can you tell me what will happen if I do a passive pull-down of that TRST
input, can I still use that TAP interface of that ethernet controller when
TRST is continue pull-down? I don't have the on IEEE 1149.1 spec, so I
can't find an answer on that.
By the way the ethernet controller is the LXT971C of Intel.
Can you also please send me that white paper about JTAG spec, thanks!
greetings Nico
-----Original Message-----
From: CJ Clark [mailto:cjclark@xxxxxxxxxxxxxxx]
Sent: Wednesday, April 09, 2003 4:39 PM
To: 'Nico Fleurinck'; 'compactPCI (E-mail)'; 'si-list'
Subject: RE: TRST signal of JTAG I/F
Hello Nico,
You don't really tell us the context of your question, and that is
important in giving you the right answer. If you are designing an
ASIC, it's quite clear that TRST should have an internal pull-up.
At the PCB assembly level, you have multiple approaches for handling
TRST (and the other 1149.1 signals for that matter) depending on
whether you are designing a cPCI backplane, cPCI daughter card or
just stand-alone PCB.
In general, TRST is an active low signal. At the PCB/System level, TRST
should be low at least once during power-up. Devices on PCBs that
have a TRST pin need to have their TAP controllers initialized and using
TRST to do this is easier than clocking TCK 5 times and holding TMS high.
The simplest approach to doing this is to have a pull-down on TRST. This
is the passive approach and guarantees that TRST was 'low' at 'least once'.
AND IT IS CORRECT! I understand why you are confused because several
companies out there, some claiming to be 'JTAG experts' have distrubuted DFT
guidelines and say pull-up on TRST. This is absolutely wrong, and contrary
to the standard. They may be confusing the TRST pull-ups INSIDE of an IC
with the PCB level implementation.
Now, you could have a pull-up on TRST as shown in Figure 6-8 of the 1149.1
standard (5-8 in the old standard), but this is only inconjunction with
active circuitry such as the power-up reset generator shown. This might be
where people are confused, that figure uses TRST pulled high at the PCB
level because it is fed into an AND gate, the other input from the POR
generator, the 'low' is generated by the POR circuitry. The output of the
AND goes to TRST of the devices. This method has the advantage that it
doesn't consume as much power as the passive pull-downs. But, if you are
totally doing this with passives, the answer is pulled-low. The ICs HAVE to
see a logic low on TRST at sometime during powerup, otherwise their TAP may
come up in a strange state and potentially lock up (and this can be VERY
difficult to Debug/Diagnose when your system randomly doesn't come up).
Now how you implement this would also depend on what you are designing. If
it is a cPCI daughter card, consider the accumulative effect of each card
having a pull-down, the current draw will be greater and potentially you may
have difficulty driving the TRST high if you wanted to do something like
configuration or 1149.1 test. The best method would be to have the TRST
pulled-low on the backplane, however, this would have to be part of the cPCI
spec (and it is not. Heck, the whole 1149.1 interface is wrong in cPCI, but
this has continued to fall on deaf ears. The TDI/TDO/TMS/TCK should be
BUSSED in the backplane, TDI-TDO should NOT be daisy chained in a
backplane/system. Is there a backplane manufacturer that is willing to buck
the cPCI spec?).
If anyone is interested in a whitepaper on IEEE 1149.1/IEEE 1532
infrastructure, send me an email.
Regards,
CJ
IEEE 1149.1 chair 1996-2002
--------------------< Http://www.intellitech.com >----------------
Intellitech Corporation
70 Main Street, Durham, NH 03824 Embedded Test and
PH:603-868-7116 FX:603-868-7119 FPGA configuration
------------------------------------------------------------------
> -----Original Message-----
> From: Nico Fleurinck [mailto:nico.fleurinck@xxxxxxxxxxxx]
> Sent: Wednesday, April 09, 2003 9:50 AM
> To: 'compactPCI (E-mail)'; 'si-list'
> Subject: TRST signal of JTAG I/F
> Importance: High
>
>
> Dear experts,
> I'm confused about what I shall do when I don't use the TRST
> signal of a
> JTAG interface.
> In some documentation I found that I shall pull-it-down with
> a 4K7 resistor
> and in other documents I found that I shall pull-it-up to VCC
> via a 4K7
> resistor.
> It is very confusing.
> Can someone please tell me what I shall do.
> Of the JTAG interface I think it is enough to just use the
> TCK,TDI,TDO,TMS
> signals.
>
> Many thanks in advanced.
>
> greetings,
> Nico
>
> Nico Fleurinck
> Junior Design Engineer
> VERHAERT Satellites & Platforms
> Hogenakkerhoekstraat 21
> B-9150 Kruibeke
>
> Tel : +32 3 250.1984
> Fax : +32 3 254.1008
> e-mail : nico.fleurinck@xxxxxxxxxxxx
> Visit us : www.verhaert.com
>
>
>
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