[SI-LIST] FW: Re: via-in-pad technology
- From: "Chris Chalmers" <cchalmers@xxxxxxxxxxx>
- To: <darshanmehta2k@xxxxxxxxx>
- Date: Thu, 11 Nov 2004 12:05:03 -0000
Darshan,
Also
Please see the archives for via in pad technology.
I have attached one of them. The excellent response
to partically the same question is given by Sol Tatlow.
His response was pretty thorough.
Chris
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Sol Tatlow
Sent: 07 May 2004 13:50
To: greg.e.inchauspe@xxxxxxxx; Si-List
Subject: [SI-LIST] Re: via-in-pad technology
Hi Greg,
a 1704 pin BGA ... that's a big sucker (have fun ;-)!), possibly the
Xilinx Virtex II Pro FPGA? Anyway, attached are a few mails on the via
subject from a few weeks back (see also SI archives).
The short (but unhelpful) answer:
Via-in-pad or microvias from a GOOD PCB house will be MUCH better
than normal vias from a BAD one, and give you more flexibility, and in
the case that you have a tried and tested PCB manufacturer who can do
this, I wouldn't worry about such problems, if you NEED these techs.
We (ProDesign) regularly mount such BGAs (on good boards!) problem-free.
The longer answer:
Ignoring the fact that you didn't specify under what conditions the
boards/chips will be used, whatever techs you use to reduce layer count/
increase packing density (incl. 'simply' sub 4 mil/100µ tracks/gaps),
it will only be as good as the manufacturer producing the boards. This
sounds obvious, but a) they might not tell you they have little
experience with a particular process, or b) they may not even know
themselves, despite quality controls/certification, if there is a newly
developing problem somewhere in the process line due to inexperience.
Usually, you discover this the hard way, when a) a board isn't delivered
on time (since all boards have failed the e-test), b) the boards are
defective after soldering, or even worse, c) the boards fail in the field
after just weeks or months 'in action'. I mean, sure, there are quality
control processes/certifications (which Lockheed Martin must require in
any case, right?), but long term in-the-field 'tests', specifically with
such high pin count BGAs are going to be hard to find.
My advice: talk with potential MANUFACTURERS, to see if they can provide
you with references for similar boards (customers who can provide a
quality statement). They can hardly object to this, and if they do, or
can't provide you with such references, I would assume you will be their
'lab rat' for extending their capabilities, or at least for furthering
their experience with such technologies (unfortunately, this is likely,
with such a large BGA).
My opinion: my densest board is a 24,000 pin design on ~320x132mm area.
This equates to nearly 400 pins per sq inch, incl. 3 XC2Vxxxx 1517
pin BGAs. I used NORMAL via tech to route this on 18 layers, and the
manufacturer (www.eltek.co.il) produces this board (incl. 16,500 vias
per board) WITHOUT rejects (I KNOW this for sure!). It also performed
beautifully (1st time!). i.e. are you SURE that special PCB techs are
necessary? For example, with 500µ via pad/100µ track/spacing/2mm board,
you should be able to route even a 1704 pin BGA on 18 layers without
special techs - if you have no need to use the space under the BGA for
more than 'chicken feed' (decoups, termination, etc.), I would go for
this solution (attention should as always be paid to good DFM points).
My 'recommendations': although I have never had boards manufacturered at
either of the following PCB houses, so I can NOT vouch for quality, I CAN
vouch for helpful technical advice (even when they have no financial
interest in helping), PLUS, such HDI technologies are DEFINITELY not new
to them:
www.westwoodpcb.com (lots of PDFs to download!)
www.multek.com (a number of different fabs for different requirements)
I suggest these as american sources, from the point of view of a
european - my daily experiences are with german, english, swiss and
israeli houses, and if asked for PCB houses here, I have other names.
Summary of the above 'novel': with the right manufacturer, you can be onto
a winner, with regards to achieving minimal proportions and max performance
with the use of HDI, but until you are sure you have a good manufacturer,
be careful, and be REALLY critical about whether you NEED or BENEFIT from
such technologies - if not, don't (b.t.w. I have lots more info on the
subject, incl. a list of when to use and when not to use HDI - contact me
if this is of interest to you - I figured this mail was too long already!)
____________________________________
Sol Tatlow, M.Eng. (Oxon)
ProDesign Electronic & CAD Layout GmbH
Product Developer
Albert-Mayer-Str. 16
D-83052 Bruckmuehl
Phone: +49 (0) 8062-808-302
Fax: +49 (0) 8062-808-333
Mailto:sol.tatlow@xxxxxxxxxxxxxxxxxxxx
www.prodesign-europe.com
____________________________________
-----Ursprüngliche Nachricht-----
Von: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] Im
Auftrag von Inchauspe, Greg E
Gesendet: Donnerstag, 6. Mai 2004 23:04
An: Sig Integ Group
Betreff: [SI-LIST] via-in-pad technology
Hello SI group,
I'm considering using via-in-pad or via fill technology to mount a 1704 pin
BGA. Does anyone have any experience with using this technology for large
BGA's? I've heard that there are potential thermal problems that can cause
the via barrel to crack.
Thanks,
Greg
-- Attached file included as plaintext by Ecartis --
Reply-To: "Sol Tatlow" <Sol.Tatlow@xxxxxxxxxxxxxxx>
Hi Chris,
>Is it ok to put vias actually on the pads of
>a ceramic decoupling cap in terms of manufacture?
>Do other people do this?
yes, you CAN do this, BUT it can require technologies
(micro-via or via-plugging techniques) that are
otherwise not needed - this can make the PCB more
expensive, as well as extending delivery times, plus
can limit your choice of PCB manufacturers: it is NOT
simply a case of placing normal vias in pads at the
layout stage and end of story (solder paste disappears
into the holes=3D3Dbad/no joints, solder paste application
difficulties on other side, etc.).
Obviously, via-in-pad CAN give you the best technical
result/performance with very small decoupling caps,
where there is no space to put the vias for the
individual pads BETWEEN the pads (0603 and smaller),
and in the case of micro-vias allows the placement
of caps directly under full matrix BGAs where it might
otherwise not be possible (good against 'bounce'),
but needs to be weighed against cost requirements.
On a more detailed level, before you use something like
micro-vias, you perhaps also need to do analysis
(comparison) of the impedances of the various
possibilities of connecting the pads to the planes,
since micro-vias are (obviously!) small. Plus, micro-
vias (normally) only connect between neighbouring
layers - stacking is possible, but EXPENSIVE! - which
means they are perhaps ok for GND (L1-L2) but not
for PWR (L1-Lx).
Plugging is yet another different story, with different
methods and (plugging) materials.
If you want more info, let me know, and I can give
you more info on manfg. techniques that will help
you evaluate the pros and cons.
Hope this helps!
____________________________________
Sol Tatlow, M.Eng. (Oxon)
ProDesign Electronic & CAD Layout GmbH
Product Developer
Albert-Mayer-Str. 16
D-83052 Bruckmuehl
Phone: +49 (0) 8062-808-302
Fax: +49 (0) 8062-808-333
Mailto:sol.tatlow@xxxxxxxxxxxxxxxxxxxx
www.prodesign-europe.com
____________________________________=3D20
Hmmm .... plugging .... well, there are lots of different
kinds, including: take a look at
http://www.chipit.de/ce/CHIPitPlatinumEdition.htm#
to see one of the several types of products (ASIC verification)
I am involved in (featuring 25,000 pin boards with 18 layers,
where I am proud to say, ONLY 18!) - PCB design, product
packaging, 3D virtual modelling and certification were my main
domains with this product.
Apart from cheap self-promotion ;-), plugging (of the PCB
kind) is a whole specialist area in itself, which can be
used for one or more of several purposes:
1. filling of normal through hole vias to allow a board
to be tested on a vacuum ICT machine;
2. filling of micro-vias to provide a flat solderable
surface (via-in-pad) for BGAs (or in this case, decoups -
Vincenzo, it has nothing to do with the PCB fab house,=20
rather the ASSEMBLY guys, where the SOLDER PASTE will
otherwise disappear into the hole =3D no joint!);
3. filling of blind and buried vias to prevent manufacturing
defaults (exploding vias during soldering, long-term
after-etch problems, etc).
Materials used vary from non-conductive resin compounds to
conductive silver compounds, 'solid' or liquid - what type of
compound used will depend upon the cost/volume/purpose
combination: an interesting, almost side-effect of conductive
plugging can be the reduction of resistance/impedance of a=20
through board connection - although at high frequencies the
skin effect reduces this 'handy' effect, this still has uses
in heat transfer (from one side of PCB to other) and in
relatively low frequency/high current areas like switch mode
PSUs.
Processes used to be mainly screen or stencil but there are
now others such as Roller Coating that enable relatively high
PCB-thickness-to-hole-diameter aspect ratios (>15), as well as
much more reliable internal (buried) via plugging.
In general though, plugging used in combination with micro,
blind and buried vias always increases complexity and
price of a board, and is therefore usually reserved for
really high density designs, but it can mean a reduction
in the number of layers used, which in boards with high
layer counts might make the difference between possible and
impossible - typical applications include boards with high
density BGAs on one side, and fine pitch high density SMD
connectors (like the 'BGA' types available from SAMTEC - an
utterly brilliant connctor company) on the other. In some
cases you can also expect performance bonuses.
A good start point for microvias:
http://www.circuitree.com/CT/FILES/HTML/PDF/how-to-get-started-HDI.pdf
and one for plugging:
http://pcdandm.com/pcdmag/mag/0403/0403kramer.pdf
One last thought: while such via and plugging techniques can
enable a great PCB Layouter to work wonders, without that great
PCB Layouter (MUST get into the habit of saying PCB Designer!),
and I DO mean PCB Layouter, NOT auto-router (!!!) to decide when/
if/how to use them, they will only increase your costs and give
you some major headaches!
Happy plugging ;-) !!
___________________________________
Sol Tatlow, M.Eng. (Oxon)
ProDesign Electronic & CAD Layout GmbH
Product Developer
Albert-Mayer-Str. 16
D-83052 Bruckmuehl
Phone: +49 (0) 8062-808-302
Fax: +49 (0) 8062-808-333
Mailto:sol.tatlow@xxxxxxxxxxxxxxxxxxxx
www.prodesign-europe.com
___________________________________
Dear Sol,
I would definitely like to hear more about plugging.
I bet others would too, so please post any further
thoughts and/or information on the entire reflector.
Thanks.
Regards,
Paul
_______________________
Sol Tatlow wrote:
> Hi Chris,
>=20
>=20
>>Is it ok to put vias actually on the pads of
>>a ceramic decoupling cap in terms of manufacture?
>>Do other people do this?
>=20
>=20
> yes, you CAN do this, BUT it can require technologies
> (micro-via or via-plugging techniques) that are
> otherwise not needed - this can make the PCB more
> expensive, as well as extending delivery times, plus
> can limit your choice of PCB manufacturers: it is NOT
> simply a case of placing normal vias in pads at the
> layout stage and end of story (solder paste disappears
> into the holes=3D3Dbad/no joints, solder paste application
> difficulties on other side, etc.).
>=20
> Obviously, via-in-pad CAN give you the best technical
> result/performance with very small decoupling caps,
> where there is no space to put the vias for the
> individual pads BETWEEN the pads (0603 and smaller),
> and in the case of micro-vias allows the placement
> of caps directly under full matrix BGAs where it might
> otherwise not be possible (good against 'bounce'),
> but needs to be weighed against cost requirements.
>=20
> On a more detailed level, before you use something like
> micro-vias, you perhaps also need to do analysis
> (comparison) of the impedances of the various
> possibilities of connecting the pads to the planes,
> since micro-vias are (obviously!) small. Plus, micro-
> vias (normally) only connect between neighbouring
> layers - stacking is possible, but EXPENSIVE! - which
> means they are perhaps ok for GND (L1-L2) but not
> for PWR (L1-Lx).
>=20
> Plugging is yet another different story, with different
> methods and (plugging) materials.
>=20
> If you want more info, let me know, and I can give
> you more info on manfg. techniques that will help
> you evaluate the pros and cons.
>=20
> Hope this helps!
> ____________________________________
> Sol Tatlow, M.Eng. (Oxon)
> ProDesign Electronic & CAD Layout GmbH
> Product Developer
> Albert-Mayer-Str. 16
> D-83052 Bruckmuehl
> Phone: +49 (0) 8062-808-302
> Fax: +49 (0) 8062-808-333
> Mailto:sol.tatlow@xxxxxxxxxxxxxxxxxxxx
> www.prodesign-europe.com
>
Hi folks, once more to the breach ;-) ... (it's LOOONG, but there's
an interesting point towards the end!)
Vincenzo: plating vias shut is a BAD idea! - like Ivor says, it
is most likely (regardless of via size) that the via will first be
closed at the top and bottom before it closes in the middle, since
the reduction in diameter of the via top and bottom naturally reduces
the flow of liquid to the middle of the via. This results in the
likelihood of fluid and/or gas left in the centre of the via, and
THIS results mostly in exploding vias, or in the case of small vias,
simply no reliable plating in the centre of the via. With a high
via count, this effect will more or less guarantee the rejection
of every single board, either at fab or assembly. Additionally,
as with filling holes with solder at PCB fab, you will not get a flat
surface on the outer layers, which is bad for fine pitch SMD components.
Larry: what you say is MOSTLY correct -
The main cost is in the extra process, and not only that,
but the number of manufacturers that can reliably do this
is naturally smaller than those who can't, and they generally
have a higher price, but whether you then use 1,000 or 1,200
is pretty irrelevant, EXCEPT perhaps for high volume production.
Plus, when a pin has 4 microvias in it, instead of only 1, there is
less of a chance that this pin will not be connected through faulty
via production (lower reject ratio)! Not to mention the inherent
reduction in impedance of the connection ... BUT, you must differentiate
between a microvia that goes from L1-2 and one that goes L1-X (which
usually requires a (X-1)-step process, dependent upon diameter -
'stacking'), and _that_ DEFINITELY costs more.
George/Steve: Filling vias with solder paste is possible, as Larry
already experienced, and is a function of pad size (therefore the
area of solder paste that is applied), via hole size, board thickness
but ALSO solder STENCIL thickness - this thickness can be varied (sub
100=B5 up to 400=B5). HOWEVER, with double-sided reflow, you can get
problems on the 2ND side, not with re-wetting of already present
solder (that's what solder pastes with different melt temperatures
are for), but where the solder has filled the vias and left small
'pips' that stick out of the bottom - this makes it difficult to apply
solder paste to the bottom side, because the stencil doesn't sit flat
on the board. So for single-sided boards, or reflow-wave combinations,
this might be fine, but almost certainly not for double-sided reflow -
again, something that a decent PCB designer with good production
knowledge can address right at the start.
X2Y caps: it would be interesting after the last 0603 test board to
see a test board with microvias - my bet is, you will see an EVEN more
drastic comparison to normal caps, since the impedance of the extra
routing (a large common factor) drops.
FINALLY - DEFINITELY the most interesting possibility for microvias:
This is not immediately obvious, as it is fairly radical - instead
of the usual L2 and L(X-1) as GND planes, you connect all NON-
GND SMD pads on outer layers using microvias to the next inner layer,
and the OUTER layers are flooded with GND - this MASSIVELY reduces
the 'peppering' of the inner planes with GND pads/anti-pads, thereby
FURTHER reducing the impedance of the other PWR planes and leaving
LOTS more room for routing on the inner layers - hence the possibility
of reducing overall layer count. L2 to L(X-1) can be connected with
normal vias before the outer 2 foil layers are added. Of course the
GND 'planes' on the outer levels must be connected with each other,
and probably with other GND planes in the board, but the number of
vias necessary for this is far smaller than otherwise needed, and more
to the point, you are FLEXIBLE with regards to where these are! For
small, dense 4 layer boards this can have AMAZING results! PLUS, on
thick boards, this reduces the overall thickness of the board that
must be through-drilled by maybe 200=B5 or more, which ALSO increases
drilling reliability and reduces reject rates.
Phew, I'm through now ... but the next time, someone buys me a beer
first, so I don't get a dry mouth from talking so much ;-) !
____________________________________
Sol Tatlow, M.Eng. (Oxon)
ProDesign Electronic & CAD Layout GmbH
Product Developer
Albert-Mayer-Str. 16
D-83052 Bruckmuehl
Phone: +49 (0) 8062-808-302
Fax: +49 (0) 8062-808-333
Mailto:sol.tatlow@xxxxxxxxxxxxxxxxxxxx
www.prodesign-europe.com
____________________________________
=20
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