## [SI-LIST] Re: FW: Re: via capacitance

• From: Istvan Novak - Board Design Technology <inovak@xxxxxxxxxxxxxxxxxxx>
• To: justin.tabatchnick@xxxxxxxxx
• Date: Wed, 17 Jul 2002 18:03:02 -0400 (EDT)

```Justin,

Re Q1: the question is valid, and in general, it depends on the geometry.
Because
only narrow segments of the pads carry the high-speed current, the first-cut
model
for the pads is a capacitance.  The via barrel does carry the high-speed signal
between the connecting layers, so it could be either capacitive or inductive.
Here
we may want to look at typical geometry numbers (and eventually you can go
through
the same thought process with your numbers). On dense boards today the trace
width
could be as narrow as 4 mils (0.1mm), sometimes even less.  If these traces are
connected to a plated through hole, taking a connector pin, the drill size may
need
to be as big as 26 mils (0.66mm) or more (note 1: for capacitance calculations
it
is the outer diameter of the metal cylinder what matters.  Note 2: By some
definitions the plated through hole taking a component lead is not a via, but
the
electrical function and model are similar.)  The pad and clearance hole
diameters
are typically the drill_size plus a constant, which results in lower equivalent
impedance for bigger drill sizes. A transmission-line section with lower
characteristic impedance looks more capacitive. As pads are mostly capacitive,
and
barrels on fine-pitch boards tend to be more capacitive then inductive, the net
result on fine-pitch boards tends to be (but of course it is not always) a
capacitive effect, unless intentionally it is compensated for by either
suppressing
unused pads, increasing clearance holes, or by some other layout tricks.

Re Q2: Assuming that the net effect of the via is capacitive, this means that
its
equivalent impedance is lower than that of the surrounding traces.  If say the
trace impedance is 50 ohms, you could start out modeling the via with a 50-ohm
segment and propagation delay matching the time of flight between the
transitioning
layers. In my previous example for a side-to-side transition on an FR4 100-mil
board, it would be an 18ps 50-ohm interconnect.  This already has some
capacitance
in it (0.36pF in the example), but so far this would not create any
reflections.
To bring the impedance of this segment down to the estimated via impedance, we
can
connect the additional capacitance in form of a discrete capacitor to the via
circuit (0.14pF in the example, assuming that the actual 'total' via
capacitance
was 0.5pF). This discrete capacitance WILL create reflections, and it is this
effect that usually we want to capture in signal-integrity simulations.  IF now
we
took out the 50-ohm 18ps interconnect from the model, we would still have the
0.14pF discrete capacitance connected to the 50-ohm traces.  The signal
distortion
effect of the via is still captured, we only miss the 18ps delay from the total
time budget. Gbps interconnects tend to be using clock forwarding or embedded
clock, so the absolute delay matters little, the emphasis is on high-frequency
reflections and attenuations.

Re Q3:  You are correct in saying that stub impedance is periodically
capacitive/inductive as frequency varies. Note that the entire discussion above
assumes that we are in a region of frequencies and dimensions where the lumped
approximation of the via is valid.  If we take an FR4 250-mil thick board, the
maximum straight vertical time of flight is about tpd=45psec.  The quarter-wave
resonance frequency is f=1/(4*tpd), or around 5.6GHz, which corresponds to a
bit
frequency on a 11.2Gbps signaling rate.

Regards

Istvan Novak
SUN Microsystems

Delivered-To: si-list@xxxxxxxxxxxxx
From: "Tabatchnick, Justin" <justin.tabatchnick@xxxxxxxxx>
To: "'si-list@xxxxxxxxxxxxx'" <si-list@xxxxxxxxxxxxx>
Subject: [SI-LIST] FW: Re: via capacitance
Date: Wed, 17 Jul 2002 09:53:11 -0700
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X-list: si-list

Hi Ivan ;

I found your discussion interesting and I would like to know how you
arrived
at some of your conclusions for instance;

1) Why is the characterisitc impedance of a via transitioning the board
width typically lower then that of the connecting traces ?
2) Can you elaborate more on your supposition that the difference
between
your estimated and approximated capacitance need only be simulated.
3) I thought that the impedance presented by a stub is dependent on
length
and frequency and that it could be inductive or capacitive ( also taking
into account the capacitive parasitics as it passes through the various
planes).

Thanks
Justin Tabatchnick
Intel,Sacramento

-----Original Message-----
From: Istvan Novak [mailto:istvan.novak@xxxxxxxxxxxxxxxx]
Sent: Wednesday, July 17, 2002 5:03 AM
To: howiej@xxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: via capacitance

Dear Dr. Johnson,

Thanks for posting from your upcoming book, I look forward to seeing it
in
print.
I offer the following comments on the posted pages:

1., I am sure you address this point somewhere in your upcoming book,
just
to make sure that si-list members can put the posted pages properly into
context: vias, like any other interconnects, are inherently associated
with
some capacitance, inductance, resistance.  This is fact of nature, and
not
necessarily bad.  In a lossless interconnect, they set the
characteristic
impedance as Zo=sqrt(L/C) and the propagation delay as tpd=sqrt(L*C).
On a
matched trace, we dont need to worry about any large amount of trace
capacitance or trace inductance, as long as the Zo and tpd numbers are
acceptable.  The same applies to vias and through holes: if the entire
length of the barrel carries the signal (we make the tranition between
the
two outer layers) our only goal is to set the equivalent inductance and
capacitance of the via to create a characteristic impedance that
matches
the
characteristic impedance of the connecting traces. One good article
showing
techniques to achieve this is: Danial G.Swanson, "Optimising
Transitions in
Multilayer PC Boards," Proceedings of Workshops at IEEE MTTS, 11-16
June,
2000, Boston, MA.

What really matters for high-speed signaling purposes is the deviation
from
this ideal situation.  This can happen in two ways: the via impedance
may
not match the trace impedance, or not the entire length of the via
carries
the signal (or a combination of these two).  In the first case, having
a
via
between the outer two layers, the equivalent via impedance typically
may be
lower than the characteristic impedance of connecting traces.  This
creates
an extra capacitance of the via, but only the DIFFERENCE (and not the
entire
via capacitance) causes reflection losses in high-speed signaling. For
instance, having 50-ohm traces and a 100-mil thick FR4 board, the
capacitance of a 50-ohm matched through via between the outer layers is
approximately 0.36pF.  If the estimated via capacitance is 0.5pF, only
0.5-0.36=0.14pF lumped capacitance needs to be taken into account in
additional 0.36pF in the simulations, we should do that by inserting a
Zo=50-ohm tpd=18ps delay line in series to the traces.  In this first
case
obviously we cannot reduce the via capacitance by back drilling.  In the
second case, when there is a through via, but the signal transition is
not
between the outer two layers, the entire static capacitance of the
'UNUSED'
portion of the via (also called via stub) shows up as capacitive
In this second case backdrilling helps.

2., In the text, the via shown in Figure 5.25 is called 'blind via'.
In
my
understanding, blind vias are those, which connect from one of the
surface
layers down to one of the inner layers, so on the finished board we have
access to only one end of it, but not to the other end.  By using this
definition, the via shown in Figure 5.25 is a through via.  On the other
hand, if it was really a blind via, just additional layers on one side
of
the stackup are not shown in the figure, those  layers not shown would
have
an impact (increase) on the reported capacitance figures.

3., On page 5.2, in the description of the three possible ways to
reduce
via
capacitance, the first item is called blind via. It appears to me that
the
description refers to a buried via process.  In my understanding, the
differentiator is: if the via hole is made BEFORE final lamination, it
means
that it will end up being between inner layers at both of its ends, so
none
of the via ends is accessible or visible on the finished board.
Certainly
it
would be possible to create a blind via before the final lamination
step,
but because the extra processing step would add cost unnecessarily, I
do
not
see a reason for doing this unless the blind via must have a large
aspect
ratio (>1) that cannot be plated if created after lamination.

Best regards

Istvan Novak
SUN Microsystems

----- Original Message -----
From: "Dr. Howard Johnson" <howiej@xxxxxxxxxx>
To: <si-list@xxxxxxxxxxxxx>
Sent: Tuesday, July 16, 2002 12:45 AM
Subject: [SI-LIST] Re: via capacitance

>
> Oops! I apologize for thoughtlessly sending an attachment in
> my
> missive dated Thursday, 11 July about via capacitance.
> If you are interested, the attachment
> has been posted to:
> www.sigcon.com/pubs/news/viacapacitance.pdf
>
> Best regards,
> Dr. Howard Johnson, Signal Consulting Inc.,
> tel +1 509-997-0505,  howiej@xxxxxxxxxx
> http:\\sigcon.com  -- High-Speed Digital Design articles,
> books, tools, and seminars
>
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>

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Istvan Novak            Sun Microsystems, Inc.
Istvan.Novak@xxxxxxx    Workgroup Servers, BDT Group,
One Network Drive, Burlington, MA 01803
Phone: (781) 442 0340

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