[SI-LIST] FW: Re: Majic Fbaud/1667 for CDR bandwidth
- From: Richard Jungert <r_jungert@xxxxxxxxxxx>
- To: <swldstn@xxxxxxxxxxxx>, <weirsi@xxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Thu, 18 Sep 2008 18:27:32 -0700
Steve
Here is is.
http://www.tek.com/Measurement/App_Notes/55_16025/eng/55W_16025_0.pdf
Its in a app note in the Tektronix product. I think maybe this is the hint as
to what your looking for. Please let me know what you make of this. See the
notes around Figure 1 where it talks about Fiber Channel T11.2.
Richard Jungert
HTTP://www.rjungert.com
Excellence in Circuit Board Design
From: swldstn@xxxxxxxxxxxx
To: r_jungert@xxxxxxxxxxx
Subject: RE: [SI-LIST] Re: Majic Fbaud/1667 for CDR bandwidth
Date: Wed, 17 Sep 2008 06:40:24 -0400
Richard, There wasn?t a PDF attached or it
got filtered. Can you please resend or point me to a link.
I have the FC-MJSQ spec but it talks in
terms of Sonet and its Fbaud/2500 being recalculated to Fbaud/1667.
Steve
From: Richard Jungert
[mailto:r_jungert@xxxxxxxxxxx]
Sent: Tuesday, September 16, 2008
1:46 PM
To: swldstn@xxxxxxxxxxxx
Subject: FW: [SI-LIST] Re: Majic
Fbaud/1667 for CDR bandwidth
Steve.
Figure 1 in this PDF file may have a hint as to what your looking for. It talks
about Fiber Channel T11.2 specs and golden PLL's that reject noise below
1.5MHZ. Maybe this can help.
I did a board 2 years ago that looks exactly like the one in Figure one in this
pdf file.
Richard
From: r_jungert@xxxxxxxxxxx
To: weirsi@xxxxxxxxxx; swldstn@xxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: RE: [SI-LIST] Re: Majic Fbaud/1667 for CDR bandwidth
Date: Tue, 16 Sep 2008 09:43:36 -0700
Steve.
Bellcore-compliant systems Only data is communicated over Sonet links in both
LANs and WANs. The derivation of clock from an incoming data signal is done by
a special piece of circuitry called the clock and data recovery (CDR)
device.Jitter generation relates to both the transmit clock multiplier
phase-locked loop and the receiver phase-locked loop. In line-timing mode, a
stable clock reference distributed from either a BITS or filtered recovered
clock is used by a transmit clock multiplier phase-locked loop to generate a
bit clock. In through-timing mode, a regenerator uses the recovered clock
directly to transmit data. The jitter generated by these phase-locked loops is
usually less than 0.005 UI-rms.
Two types of CDRs are available to system designers: one with a narrow
bandwidth jitter transfer function phase-locked loop and one with wide
bandwidth.
The transfer function of the narrow bandwidth CDR stays within the Bellcore
jitter transfer specification limit while the wide bandwidth CDR exceeds the
critical frequency limit.
The narrow bandwidth CDR is the best candidate for implementing jitter
transfer-compliant systems, but there are trade-offs. As the phase-locked loop
bandwidth decreases, so does its capability to respond. A narrow bandwidth
phase-locked loop takes longer to lock onto a data stream and will not handle
as much jitter in some spectral ranges compared with the wide bandwidth
phase-locked loop.
See Belcore specs for loop bandwidths.
Hope this helps.
Richard Jungert
> Date: Tue, 16 Sep 2008 00:16:22 -0700
> From: weirsi@xxxxxxxxxx
> To: swldstn@xxxxxxxxxxxx
> CC: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: Majic Fbaud/1667 for CDR bandwidth
>
> Steve, generally in a CDR scheme we want to track at as high a rate as
> we can. We can dump the results into an elastic store and then use a
> second PLL with a lower rate to smooth out the bumps for reading out the
> elastic store and/or forwarding.
>
> I don't know why XAUI has such a tall ratio. Either there is some break
> in the 8b/10b pattern possible, or it seems to be about 50 times taller
> than it needs to.
>
> Steve.
> Steve Waldstein wrote:
> > Steve,
> >
> > Thanks for your answer but I'm still a little perplexed. In a PLL the
loop
> > bandwidth typically wants to be about a factor of 10 lower than the
> > transition density in the reference clock to the PDF. But pushing the
> > bandwidth lower will allow a noiser (more jitter) reference clock at
the
> > expense of seeing increased VCO jitter. The opposite it true where
you use a
> > higher loop bandwidth to clean up the VCO but you suffer from clock
noise
> > passing through the loop bandwidth that causes output jitter.
> >
> > I'm sure there is a similar analogy for the CDR. A lower loop
bandwidth
> > should produce a cleaner recovered clock but makes the loop less
agile to
> > data changes. A higher loop bandwidth makes the loop more agile but
produces
> > more jitter on the output.
> >
> > Lets use an example for discussion. XAUI has Fbaud = 3.125 Gb/s and
8b/10b
> > (or 10Q) encoded. Yet its corner frequency is set at 3.215/1667 1.87 MHz.
> > Is this because XAUI want to recover a clock and recreate it to some
kind of
> > PPM accuracy similar its input spec of +/- 100 PPM? I know SONET had
> > repeaters in it where the clock recreation was important but on most
serial
> > links that's not the case. So since you said Fbaud/30 was typically
> > sufficient to recover the day why burden the receiver with such a
narrow
> > loop bandwidth?
> >
> > Is it really related to the fact that at +/- 100 PPM one skip is
inserted
> > every 5000 symbols so the 1667 provides margin to this by a factor of
3?
> >
> > I've also seen calculation that predict the jitter of a sinusoidal
> > modulation of the carrier that relate to the equivalent PPM. It the
corner
> > really set to handle this type of issue? And not ability to recover
the
> > data?
> >
> > I know these are a lot of questions but your answer doesn't help
understand
> > why these standards have chosen such a low loop bandwitch.
> >
> > Steve W.
> >
> >
> > -----Original Message-----
> > From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx] On
> > Behalf Of steve weir
> > Sent: Sunday, September 14, 2008 10:38 PM
> > To: Steve Waldstein
> > Cc: si-list@xxxxxxxxxxxxx
> > Subject: [SI-LIST] Re: Majic Fbaud/1667 for CDR bandwidth
> >
> > Steve the loop B/W has to do with:
> >
> > The available repetitive data rate.
> > Reasonable phase / gain margin for the loop filter.
> >
> > Each of the various data transmission standards are different in the
way
> > that they can mess up a CDR, with the net result that many standards
> > need very tall ratios between Fbaud and Fcorner. Basically, you can
> > easily achieve very stable operation by setting Fcorner = Frepeat /
5.
> > With some care you can set it to Frepeat / 3, where Frepeat is the
> > guaranteed lowest repetitive full 1-0 cycle. For a pure 8B/10Q coded
> > link, Fcorner can be as high as Fbaud / 30 and work well.
> >
> > As Chris Cheng has bemoaned, TIE and jitter in general both get worse
> > with taller ratios as the VCO drifts ( or is disturbed by things like
> > PDN noise ) over more bit intervals without the benefit of corrective
> > feedback.
> >
> > Steve.
> >
> > Steve Waldstein wrote:
> >
> >> I know many serial specifications place the corner frequency of a
CDR at
> >> Fbaud/1667. I also know that the FC-MJSQ discusses how this was
shifted
> >>
> > from
> >
> >> the Fbaud/2500 established for SONET. What I can't find is a good
> >>
> > discussion
> >
> >> on how to set CDR loop bandwidth for new serial specification. It
appears
> >> there's some relation the desired frequency accuracy or ppm but
haven't
> >> found a good derivation. Can anyone provide a good reference
relating to
> >> choosing loop bandwidth based on desired output jitter or what
ever else
> >> helps set this corner frequency.
> >>
> >>
> >> Thanks.
> >>
> >>
> >>
> >> Steve
> >>
> >> __________________________________
> >>
> >> Steve Waldstein
> >>
> >> E-mail: swldstn@xxxxxxxxx
> >>
> >> Mobile:
(207) 749-6260
> >>
> >> Home: (207) 885-0594
> >>
> >>
> >>
> >>
> >>
> >>
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>
>
> --
> Steve Weir
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