[SI-LIST] FW: RE: DDR2 design

From: "Dhiraj Kiran" <Dhiraj.Kiran@xxxxxxxxxxx>
To: <ivorlist@xxxxxxxxxxx>
Date: Tue, 28 Feb 2006 12:04:44 +0530
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        charset="US-ASCII"
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Hello Ivor,
=20
Sorry...The diagram below has a small mistake. The clocks and data
strobes are shown as 50 Ohms signals in the diagram. This is wrong.
=20
=20
The clocks CK/CK#  are routed as a 100 Ohms differential clock. The
diferrential clock pair is split into 4 branches(To the 4 DDR2 chips) at
the controller end.
=20
All the 4 differential branches are length matched. Each of the clock
limbs is individually terminated to the terminating voltage with a 50
Ohms resistor as shown in the=20
=20
diagram below.
=20
=20
The DQS/DQS# strobes are also routed as 100 Ohms differential signals.
=20
Best Regards,
Dhiraj

________________________________

From: Dhiraj Kiran=20
Sent: Tuesday, February 28, 2006 11:35 AM
To: 'ivorlist@xxxxxxxxxxx'
Cc: si-list@xxxxxxxxxxxxx
Subject: RE: [SI-LIST] DDR2 design
Importance: High



Hello Ivor,

I had a similar x64 DDR2 requirement in one of my designs.

I used 4 nos of x16 devices with the following topology. The same
topology should work for you as well.

But I would advice you to simulate.

=20

Best Regards,

Dhiraj

-----Original Message-----

From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx
<mailto:si-list-bounce@xxxxxxxxxxxxx> ] On Behalf Of Ivor Bowden

Sent: Thursday, February 23, 2006 4:52 AM

To: si-list@xxxxxxxxxxxxx

Subject: [SI-LIST] DDR2 design

Hi SI Experts,

I am reviewing a layout for an embedded DDR2 design using 4 Micron DDR2
chips with an Altera Cyclone controller. The memory is set up to be 64
bits wide, 16 bits per chip.

The target rate is 167MHz. The design is not simulated.

Termination is as follows:

ODT may be supported, still investigating.

There is no series term.

There is 0.9V stub term for control lines.

There is a differential 100 ohm term for each clock pair (4 total).

Routing is as follows:

Control lines are daisy chained and length matched between the first
DRAM and controller (about 1"), each DRAM (about .75") and the last DRAM
and terminators (about .25"); total net length is about 3.5".

Data lines are length matched at about 3" (controller to DRAM).

Clock lines are length matched at about 4" (controller to DRAM).

Trace impedance is targeted at 100 ohms for clock and control lines, and

75 ohms for data lines.

Is this design likely to work? If not, what changes should be
considered?

I very much appreciate all comments. Thank you!

Ivor Bowden

Engineer

Curtiss-Wright Controls

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=20




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[SI-LIST] FW: RE: DDR2 design

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