[SI-LIST] FW: Decoupling for PLL (continued)
- From: Geoff Stokes <gstokes@xxxxxxxxx>
- To: "'si-list@xxxxxxxxxxxxx'" <si-list@xxxxxxxxxxxxx>
- Date: Fri, 3 Sep 2004 09:38:38 +0100
Hello Zhangkun
It may be that Al Neves was pointing you in the right direction, and you
should look closely at the sidebands and possible coupling paths.
It reminds me of a radio receiver LO synth (PLL) problem I had some years
ago. The divider, working at around 1GHz initially used a pre-scaler chip
in a DIL package (!). The decoupling used chip capacitors, but the package
lead inductance would be larger than a typical SMD package. The division
ratio was 64, producing an output of about 15 MHz suitable for input into
the lower frequency PLL circuit: divider, flip-flop phase detector working
at around 1 MHz or less, and loop filter amplifier. The loop filter drives
the VCO. The receiver was desensitised for a reason that was difficult to
find, until it was realised that a harmonic of the 15 MHz fell in the
receiver IF band. I developed a theory that somehow this might be leaking
into the IF in an unexpected way. A high pass filter at the VCO output
showed that the effect was not due to direct low frequency coupling (15 MHz
etc) in that path. In another crazy experiment, I ran the RF connection to
the prescaler as a connectorised cable. I inserted a 1 GHz ferrite isolator
which would be expected to attenuate RF signal flow in the reverse direction
from the VCO. The sensitivity improved. Now, a loose coupling on the VCO
output to a spectrum analyser showed that there were in fact low level
sidebands, spaced at 15MHz and harmonic multiples. Further test showed that
the harmonics were generated in the prescaler: the common power supply
connection (and possibly the ground connection)which is inductive in the
package, was coupling the output 15MHz square wave to the prescaler input
stage, where it was mixed with the RF to produce the sidebands. This took a
very long time to find.
Cheers
Geoff
> -----Original Message-----
> From: Zhangkun [mailto:zhang_kun@xxxxxxxxxx]
> Sent: 03 September 2004 06:53
> To: si-list
> Subject: [SI-LIST] Decoupling for PLL (continued)
>
>
> Dear all
> Recently, I have done some measurement. It is found that when
> the bead(inductor) is used, the power ground noise at 333KHz
> from VRM is larger. There is some noise near the clock
> frequency points.
>
> For example, the output clock of PLL is 50MHz. At 50.333MHz
> and 49.667MHz, there is noise, which is in proportion to the
> noise at 333KHz. Maybe the PLL modulates the noise of VRM
> into the output clock.
>
> Is there any SPICE model for PLL?
>
> Best Regards
>
> Zhangkun
> 2004.9.3
>
>
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