[SI-LIST] Re: FW: AC Blocking capacitor relative positions andreference plane voids
- From: "Tom Dagostino" <tom@xxxxxxxxxxxxx>
- To: "'Lee Ritchey'" <leeritchey@xxxxxxxxxxxxx>, "'Robert Haller'" <rhaller@xxxxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Wed, 18 Nov 2009 17:08:30 -0800
Lee, making return loss specs or not making it is visible but not
significant? Yes, we have seen this.
Tom Dagostino
Teraspeed(R) Labs
13610 SW Harness Lane
Beaverton, OR 97008
503-430-1065
503-430-1285 FAX
tom@xxxxxxxxxxxxx
www.teraspeed.com
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
401-284-1827
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Lee Ritchey
Sent: Wednesday, November 18, 2009 4:44 PM
To: Robert Haller; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: FW: AC Blocking capacitor relative positions
andreference plane voids
This could be one of those cases where the effect was visible, but not
significant.
> [Original Message]
> From: Haller, Robert <rhaller@xxxxxxxxxxxxx>
> To: si-list@xxxxxxxxxxxxx <si-list@xxxxxxxxxxxxx>
> Date: 11/18/2009 1:34:29 PM
> Subject: [SI-LIST] FW: AC Blocking capacitor relative positions
andreference plane voids
>
> JF,
> Depending on your specific high speed link requirements, voids under
the
capacitors are an easy way to reduce the impedance discontinuity. We model
this with a 3D Full Wave field solver. We also built up some structures in
the lab and measured them (both in time and frequency Domains).
> We were pleasantly surprised how much the reliefs helped and how well the
correlation to tools were. I wouldn't worry about the difference between a
two cutouts versus a single void. If you can make the capacitor look like a
100Ohm transmission line (with no impedance discontinuity) then the
placement isn't critical, but in practice it depends. I have seen some
vendors specify lengths to avoid, because if the package length plus
distance to the cap (and the associated discontinuity) are a multiple of
the UI (unit interval of the LINK) undesirable resonances can occur.
>
> Regards
> Bob Haller
>
>
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of jean-francois hasson
> Sent: Wednesday, November 18, 2009 4:04 PM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] AC Blocking capacitor relative positions and reference
plane voids
>
> Hi,
>
> When looking at AC coupling capacitors on high speed serial links it is
> often recommended to void the reference plane under these capacitors to
> minimize capacitance variations. Most of the times, in the designs I
> have seen, the void is exactly underneath each AC blocking capacitor
> including landing pads. If ever the capacitors were quite close, would
> there be any reason why a single void below both capacitors would be an
> issue ? I have also noticed that most of the times AC blocking
> capacitors are not as close as possible to a transmitter or receiver
> where I thought it was beneficial to do so to remove the number of
> impedance disruptions ? Could anyone provide me with some explanation ?
>
> Best regards,
>
> JF
>
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