[SI-LIST] Re: FPGA SERDES for newer links
- From: Heyfitch <heyfitch@xxxxxxxx>
- To: "N. Paul Taddonio" <paul.taddonio@xxxxxxxxxxxxxx>
- Date: Tue, 28 Sep 2010 11:16:24 -0700
Paul,
to gain a better insight into FPGA vendor's roadmaps and
"need-to-know-basis" password-enabled features, you could try to leverage
FuturePlus partnership with Agilent and Tektronix. A 3-way NDA is what
comes to mind.
Vadim
On Tue, Sep 28, 2010 at 9:16 AM, N. Paul Taddonio <
paul.taddonio@xxxxxxxxxxxxxx> wrote:
> All:
> We need to receive DisplayPort 1.0 , 1.1 and USB 3.0 serial link signals.
>
> These new serial links pose several challenges to the receiver:
>
> 1) Spread spectrum operation
> 2) Ref-clock-less interface ( ie there is no reference clock connection
> between TX and RX)
> 3) A need to tolerate more hi freq jitter than in older serial interfaces
> such as XAUI
>
> Companies like PMC Sierra and Vitesse have in the past provided discrete
> SERDES transceivers
> but have nothing suitable for this. Other companies such as National do
> have new SERDES chips but they
> are limited capability in terms of freq range covered or programmable
> features.
>
> So we always look to FPGAs for access to new, off the shelf, flexible
> SERDES.
> Unfortunately we are a small company and getting real information from FPGA
> vendors
> about their SERDES capabilities is like pulling hen's teeth.
> Particularly when we need information that is outside of mainstream
> applications.
>
> Can anybody comment on using FPGAs to receive the new breed of serial
> standards mentioned above?
>
> Sincerely,
>
> Paul Taddonio
>
>
>
> Lead Product Design Engineer
>
> FuturePlus Systems
>
> 603 471 2734 ext. 19 (phone)
>
> 603 471 2738 (fax)
>
> www.futureplus.com
>
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