[SI-LIST] FLASH & SDRAM priority in routing
- From: "lingomoorthy" <lmoorthy.nimbeon@xxxxxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Thu, 5 Nov 2009 15:10:02 +0530
Hi Friends,
We have FLASH & SDRAM in our design and we planned to route ADD & MEM
signals to these devices from FPGA as daisy chained. Is there any priority
in between these devices (FPGA to FLASH and to SDRAM or FPGA to SDRAM and to
FLASH ) to get routed in daisy chain method. If so please let me know the
reason behind.
Thanks,
Lingamoorthi
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