hi Vipul, SMT decaps have quite high shunt leakage resistance so a few/several hundred of them are unlikely to provide a resistive leakage path between your pwr/gnd. If you were looking at on-chip decaps, this would be a different story. More likely, you are getting a very low power rail impedance at two frequencies, which are likely separated by a ratio of about sqrt(10). This effect is what people sometimes call the "big V", or in your case the "big W". We have repeatedly found you can craft a more broadband low impedance for a power rail with a lot fewer decaps if you allow more than just two values (better performance and lower cost simultaneously). How do you select the decap values to use? Try the following: (1) Determine the average loop inductance of a decap looking into the power rail from your devices. With analysis tools you can short circuit a typical decap for a typical device and look at the low frequency inductive power plane impedance to extract this loop inductance. With experience you might be able to make an informed guess but you will find significant dependence on stack-up, spacing from the devices and especially on mounting connections to the power planes. (2) Recall decaps for a series RLC resonance, with resonant frequency inversely proportional to 1/sqrt(L_loop*C_decap). Remember to include the decap ESL in this L_loop value. (3) Select decap values to cover the desired switching frequency range with these series RLC resonances. You'll find a practical upper limit to the upper frequency (i.e. very small valued caps). Now, where do you place these different valued decaps? You either guess or you can apply an analysis tool. To honor the non-commercial spirit of this forum, I'll contact you offline to discuss which analysis tool would be ideal for this application. If the spectrum of your noise is not uniform (as you might find with synchronous switching circuits, e.g. memory) you may need to craft a power rail impedance that is lower at frequencies where your system noise generation sources exist. This is analogous to crafting an RF filter response. This task can be prohibitively difficult to accomplish without detailed power integrity analysis tools. best regards, -Brad > -----Original Message----- > From: si-list-bounce@xxxxxxxxxxxxx > [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Vipul Badoni > Sent: Tuesday, November 25, 2008 2:18 PM > To: si-list@xxxxxxxxxxxxx > Subject: [SI-LIST] Experience with Power supply collapse on > boards due to excessive decoupling. > > Hello SI-Folks, > > I was wondering if some of you could share with me your > experiences with power supply collapse due to excessive > decoupling of only a few values of capacitor on boards > drawing a lot of switching current. The situation I am > dealing with has ~400 in number of 0.1uF caps and ~200 in > number of 1uf caps. The power supply shows a lot of noise ~400mV. > > Regards, > Vipul Badoni. ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List technical documents are available at: http://www.si-list.net List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu