[SI-LIST] Re: Ethernet simulation question
- From: Bob Patel <whizplayer@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Tue, 9 Jan 2007 19:55:07 -0800 (PST)
Mike, As you have discovered that the vendor will not be able to supply you the
models for the analog i/o i.e. i/o driving the Rj45.
What I would suggest is this based on the failures you mentioned:
1) I would take the link form the Phy to Rj45 & run sims to figure out the
Insertion loss for the PCB traces + vias in the path.
2) Now based on the loss you can easily figure what will be your amplitude
drops.
Since you are running 1000base-t, you will need to know what are the loss
numbers at 62.5Mhz.
3) In the IEEE 802.3ae 2005 I believe Section 3 you will find the allowable
loss budgets for the link. Compare your sims to this allowable loss and see
where the link loss is.
4) Since the IEEE tests say for the amplitude run a sequence of symbols you
can caluclate based on the symbol sequence you can caluclate the amplitude for
this waveform coming out from the PHY.
Based on the failure you are describing you might be having issues with the
lenght of your link from phy to Rj45.
Hope this helps.
Bob
agathon <hreidmarkailen@xxxxxxxxx> wrote:
Dudes,
http://www.pulseeng.com/products/datasheets/G204.pdf
May I suggest reading the pdf above.
Simulations will require models for the xfmr and cables. Could be layout &
terminations causing mismatch or cm noise issues (I don't know the
symptoms).
Simulations may not include the factors causing the degradation & so won't
be seen. Even if all is modeled, how will you track down the culprit
without knowing best practices & why ?
Doh! Now, carry on. Vedy good.
Regards,
Agathon
On 1/8/07, Fabrizio.Zanella@xxxxxxx wrote:
>
> Mike, I've run into this issue before, I pushed the vendor to provide me
> with the SPICE model for the Ethernet analog signals=2E Since in
> Hyperlynx you can link to HSPICE, I believe this is your best solution=2E
>
> Good luck,
>
> Fabrizio Zanella
>
>
>
> -----Original Message-----
> From: mkotson@miltope=2Ecom [mailto:mkotson@miltope=2Ecom]
> Sent: Friday, January 05, 2007 12:51 PM
> To: si-list@freelists=2Eorg
> Subject: [SI-LIST] Ethernet simulation question
>
> Hi all,
> I have a question regarding Ethernet simulations=2E We have a system
> that fails the Ethernet compliance tests (amplitude, rise time, fall
> time and everything associated with these) on both our 1000 Base-T and
> 100 Base-T ports=2E Due to our complicated electrical channel, the
> problem could be a number of things=2E I've been asked to do some
> simulation to determine what would be the easiest fix to make the system
> compliant=2E I contacted our silicon vendor (Intel) about models, and
> received IBIS models for both the 1000 Base-T chip (82546GB) and the 100
> Base-T chip (82562EZ)=2E Absent from both models are the Ethernet signals
> I need to simulate=2E When I asked why these pins were absent, I was told
> that they were analog signals and not part of an IBIS model=2E What is
> the proper methodology for simulating Ethernet? I'm a Hyperlynx user,
> if it makes any difference=2E
>
>
>
> I noticed a similar question was asked a few years back, but I never saw
> a good response to it=2E Thanks in advance for your help=2E
>
>
>
> Thanks,
>
> Mike
>
>
>
> Michael Kotson
>
> Project Engineer
>
> VT Miltope
>
> 4900 Pearl East Circle Suite 106
>
> Boulder, CO 80301
>
> (303) 473-0388 x132
>
> http://www=2Emiltope=2Ecom
>
>
>
>
>
>
>
>
>
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