[SI-LIST] Ethernet simulation question

  • From: "Michael Kotson" <mkotson@xxxxxxxxxxx>
  • To: <si-list@xxxxxxxxxxxxx>
  • Date: Fri, 5 Jan 2007 10:46:50 -0700

Hi all,
   I have a question regarding Ethernet simulations.  We have a system
that fails the Ethernet compliance tests (amplitude, rise time, fall
time and everything associated with these) on both our 1000 Base-T and
100 Base-T ports.  Due to our complicated electrical channel, the
problem could be a number of things.  I've been asked to do some
simulation to determine what would be the easiest fix to make the system
compliant.  I contacted our silicon vendor (Intel) about models, and
received IBIS models for both the 1000 Base-T chip (82546GB) and the 100
Base-T chip (82562EZ).  Absent from both models are the Ethernet signals
I need to simulate.  When I asked why these pins were absent, I was told
that they were analog signals and not part of an IBIS model.  What is
the proper methodology for simulating Ethernet?  I'm a Hyperlynx user,
if it makes any difference.


I noticed a similar question was asked a few years back, but I never saw
a good response to it.  Thanks in advance for your help.





Michael Kotson

Project Engineer

VT Miltope 

4900 Pearl East Circle Suite 106

Boulder, CO 80301

(303) 473-0388 x132

http://www.miltope.com <http://www.miltope.com/> 



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