[SI-LIST] Re: Ethernet PHY not linking
- From: "Suresh Subramaniam" <ssubram@xxxxxxxxxx>
- To: "steve weir" <weirsi@xxxxxxxxxx>
- Date: Sun, 24 Oct 2010 13:32:16 -0700
Steve
I wanted to throw in one additional piece of data.
Loopback with a five foot cable will link reliably at 1Gbps
The PHY is a Marvell 88e1111.
Thanks
Suresh
On Oct 24, 2010, at 1:28 PM, "steve weir" <weirsi@xxxxxxxxxx> wrote:
> Suresh 10Mbps Ethernet tolerates really severe signal and timing impairments.
> 100Mbps Ethernet is fairly tolerant especially over short distances. That
> you cannot make 100Mbps Ethernet work speaks to very basic design mistakes.
>
> You could have any number of problems:
> * Return path discontinuities
> * Severe mode conversion problems
> * Noise injection from the return path, you have AVDD adjacent to DVDD
> * Poor power quality at your transmitter and/or receiver
> * A way out of spec clock either basic frequency and/or jitter
>
> Steve.
>
>
> Suresh Subramaniam wrote:
>> Hello Experts,
>>
>> I am facing the following situation:
>>
>>
>> We have a tri-mode Ethernet PHY on one of our boards. It will reliably
>> link at 10Mbps but fails 100MBps and 1Gbps. The schematics have been
>> verified for correctness and the PHY configuration bits are strapped
>> properly on the board . RESET meets the timing specs defined in the
>> datasheet.
>>
>> The RJ-45 connector has integrated magnetics. The MDI* diff pairs out to
>> the connector are routed on the lower layers in the stackup (the last
>> five layers are reproduced below). Couple of pairs are routed on Sig4
>> and two other pairs are routed on Sig5.
>>
>> GND
>>
>> SIG4
>>
>> PWR5
>>
>> SIG5
>>
>> GND
>>
>>
>> The traces are about 0.5 inches in length. DVDD is a small plane on SIG4
>> and powers the core of the chip. AVDD is a small plane on SIG 5 and
>> supplies analog power. PWR5 is a 3.3V power plane (note that the
>> signaling voltage is 2.5V which is on a different layer). The 3.3V power
>> plane is pulled back around the RJ-45 making the MDI* diff pairs without
>> a reference plane on one side for about 100 mils.
>>
>>
>> I understand that the layout is not ideal. But can these deviations from
>> the ideal cause the link to fail at 100Mbps and 1000Mbps.
>>
>> Appreciate any pointers and insights you can offer.
>>
>>
>> Thanks
>>
>> Suresh Subramaniam
>>
>>
>>
>>
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>
>
> --
> Steve Weir
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