Are there any pitfalls in performing SI analysis when using embedded passives? Modeling the plane capacitances looks straight forward - distance between the planes, the dielectric constant, tangent loss etc... should be all I need. We are looking at products like Ohmega-Ply to provide embedded resistors. How do I model the transition from the copper trace to the resistive material, or can I ignore this transition region? best regards, David Tate Lockheed Martin Missiles and Fire Control Senior Staff Circuit Design Engineer Electrical Engineering - FPGA/Processor Design E-Mail: david.tate@xxxxxxxx <mailto:david.tate@xxxxxxxx> ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List technical documents are available at: http://www.si-list.net List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu