Hi All,
SI is one thing but EMC and RF isolation can be compromized by the
tiniest fraction of the signal energy leaking out to where it is not
supposed to be. So a device may work fine but EMC emissions and RF
performance (see Steve's message below) may not be acceptable. The
device can still work, it just costs more for shielding and other
mitigation strateges.
I have a test board I use in my seminars that models the top and bottom
two layers of a board (4 to n layers). It has two ~50 Ohm paths, one
stays on the top layer and the other spends 1/3 of its length on the
bottom layer. Exciting the signal that changes layers with little
gnd-gnd stitching (nearest is 3 inches away) results in 20% of the
applied signal amplitude showing up between the planes at the board
natural resonant frequency and the board radiates 30 dB more at this
frequency than the case where the path stays on one side of the board.
If I place a gnd-gnd via 5 mm away, 1/40th wavelength at board resonant
frequency of 248 MHz, the interplane voltage only goes down 6 dB, the
gnd-gnd via needs to be substantially closer than 1/40 wavelength for
good EMC performance.
In the final version there are six gnd to gnd vias:
1) two SMA connectors (3 inches from nearest gnd-gnd via)
2) at the 50 Ohm terminations (3 inches from nearest gnd-gnd via)
3) two at a spacing of 5mm from the signal vias
Doug
Department for Continuing Education
University of Oxford
Oxford, Oxfordshire, United Kingdom
--------------------------------------------------
Doug Smith
P.O. Box 60941
Boulder City, NV 89006-0941
TEL/FAX: 702-570-6108/570-6013
Mobile: 408-858-4528
Email: doug@xxxxxxxxxx
Web: http://www.dsmith.org
--------------------------------------------------
On Thu, 5 Nov 2015 19:04:08 +0000, "Shimko, Steve (ES)"
<s.shimko@xxxxxxx> wrote:
The use of vias has been demonstrated through both modeling and
measurements to be an absolute necessity to achieve greater than 35 db
of isolation between channels (RF traces) running on the same layer.
------------------------------------------------------------------
Steve
-----Original Message-----
From: Lee Ritchey [mailto:leeritchey@xxxxxxxxxxxxx] Sent: Thursday,
November 05, 2015 11:53 AM
To: Shimko, Steve (ES); istvan.novak@xxxxxxxxxxx;
dmarc-noreply@xxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Cc: bbakshan@xxxxxxxxx; Kevin.Hou@xxxxxxxxxx
Subject: RE: [SI-LIST] Re: EXT :Re: What's the purpose of stitching
vias which just connect one GND layer?
Once again, there are tens of thousands of designs shipping every day
with signals running at rates as high as 28 Gb/S (14 GHz) that do not
have stitching and perform very well. As I said before, most of these
products would be impossible to build if stitching was necessary for
their proper operation.
That fact that some do stitching does not demonstrate that it is
necessary nor do elaborate simulations. Once again unvalidated
simulations are worth the paper they are written on. We have way too
many people doing simulations and enforcing design constraints
without first demonstrating that the constraints are necessary.
That is simply not good engineering.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Shimko, Steve (ES)
Sent: Thursday, November 5, 2015 8:36 AM
To: istvan.novak@xxxxxxxxxxx; leeritchey@xxxxxxxxxxxxx;
dmarc-noreply@xxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Cc: bbakshan@xxxxxxxxx; Kevin.Hou@xxxxxxxxxx
Subject: [SI-LIST] Re: EXT :Re: What's the purpose of stitching vias
which just connect one GND layer?
Our RF group uses via stitching all the time. These are for 50 ohm RF
traces running on organic boards or ceramic substrates. These interfaces
are all single ended (think coax). Via stitching is also used to
create cavities where active components such as amplifiers are
located. The vias usually transverse several layers, picking up
ground planes on the top and bottom of the signal layer. They
sometimes go all the way down through the boards, though 20+ layers,
when an RF signal has to routed from the top to the bottom.
But, there also a large amount of simulation that is done when using
vias that way. Every trace, transition, and cavity is modeled using
HFSS or CST Microwave (or similar) suite of tools. With active
devices that have gain beyond 30 GHz, it is very easy to
inadvertently create resonances that can lead to oscillations and
drop-outs.
Steve Shimko
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Istvan Novak
Sent: Wednesday, November 04, 2015 7:59 PM
To: leeritchey@xxxxxxxxxxxxx; dmarc-noreply@xxxxxxxxxxxxx;
si-list@xxxxxxxxxxxxx
Cc: bbakshan@xxxxxxxxx; Kevin.Hou@xxxxxxxxxx
Subject: EXT :[SI-LIST] Re: What's the purpose of stitching vias
which just connect one GND layer?
Lee,
As always, it depends. One of the presentations our team is going to
do at DesignCon 2016 will describe (with data) a scenario when
stitching vias are needed.
Regarding the original post though, if a stitching via is attached
only to one plane layer close to the surface (ground or power) it is
prone to quarter-wave resonance, which carries its own risks.
Regards,
Istvan Novak
Oracle
On 11/4/2015 7:51 PM, Lee Ritchey wrote:
Much speculation in this message! Where is the proof?many > very high speed transmission lines without stitching vias. In
There are millions of PCBs shipped every month with who knows how
fact, > the products would be unroutable if stitching vias were
required.
(Redacted > sender "heyfitch" for DMARC)
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of heyfitch
Sent: Wednesday, November 4, 2015 11:53 AMjust > connect one GND layer?
To: si-list@xxxxxxxxxxxxx
Cc: leeritchey@xxxxxxxxxxxxx; bbakshan@xxxxxxxxx; Kevin.Hou@xxxxxxxxxx
Subject: [SI-LIST] Re: What's the purpose of stitching vias which
localized - just as the physical reality would not be localised. That
Had there been no stitching via, simulations would not have been >
is both the simulation results would be sensitive to the BC >(proximity, type...), and the diff vias (e.g.) would couple thru >
planes
and plane edges.
Worse, simulations would not be predictive of the physical reality.PM, > Lee Ritchey <leeritchey@xxxxxxxxxxxxx>
For CBCPW, you stitch to extinguish higher propagation modes, thus
preventing energy leaking into them from the diff and common modes.
Regards,
Vadim Heyfitch
Sent from my phone
On Nov 3, 2015, at 12:07, Boris Bakshan <bbakshan@xxxxxxxxx> wrote:
Best answer so far on the SI-list ! :) On Tue, Nov 3, 2015 at 9:51
wrote:cost >> of the PCB. Not much else.
Those stitching vias keep the CAD department busy and raise the
CRB >> about the stitching via.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]
On
Behalf Of Kevin Hou
Sent: Monday, November 2, 2015 9:30 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] What's the purpose of stitching vias which just
connect one GND layer?
Hi Guru:
I found one interesting thing on Intel 6-layer(S-VCC-S-S-GND-S)
path >> (GND reference transited to another GND reference) But in theThere are pairs of stitching GND via put around the differential
signals(PCIe gen3) transited from TOP to BOTTOM layer.
The differential signal is VCC reference on the TOP layer and GND
reference on the BOTTOM layer.
My understanding for the stitching via is to provide the return
Intel >> CRB I had on hand, these stitching vias are only connected
to one GND >> layer. What's the purpose?
recipient and may contain privileged or confidential information. IfUsing capacitor to connect VCC/GND will be better, right?
Best Regards,
Kevin Hou
Confidential Information:This message is sent to the intended >>
attachment.Transmissionyou received this transmission in error, please notify the sender
with a replying e-mail and delete the message and any >>
Caveat and Virus Alert:
Internet communications cannot be guaranteed to be timely, secure,
error or virus-free. The sender does not accept liability for any
errors or omissions.
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