Oh, and I forgot to add .... And what is the ratio of spacing to dielectric
thickness?
Single-ended or Differential?
In stripline?
forward or reverse crosstalk?
Trace-to-Trace or Launch-to-Launch?
Scott McMorrow
R&D Consultant
Teraspeed Consulting - A Division of Samtec
16 Stormy Brook Rd
Falmouth, ME 04105
(401) 284-1827 Business
http://www.teraspeed.com
On Thu, Nov 5, 2015 at 2:12 PM, Scott McMorrow <scott@xxxxxxxxxxxxx> wrote:
Single-ended or Differential?
In stripline?
forward or reverse crosstalk?
Trace-to-Trace or Launch-to-Launch?
Scott McMorrow
R&D Consultant
Teraspeed Consulting - A Division of Samtec
16 Stormy Brook Rd
Falmouth, ME 04105
(401) 284-1827 Business
http://www.teraspeed.com
On Thu, Nov 5, 2015 at 2:04 PM, Shimko, Steve (ES) <s.shimko@xxxxxxx>
wrote:
The use of vias has been demonstrated through both modeling and
measurements to be an absolute necessity to achieve greater than 35 db of
isolation between channels (RF traces) running on the same layer.
Steve
-----Original Message-----
From: Lee Ritchey [mailto:leeritchey@xxxxxxxxxxxxx]
Sent: Thursday, November 05, 2015 11:53 AM
To: Shimko, Steve (ES); istvan.novak@xxxxxxxxxxx;
dmarc-noreply@xxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Cc: bbakshan@xxxxxxxxx; Kevin.Hou@xxxxxxxxxx
Subject: RE: [SI-LIST] Re: EXT :Re: What's the purpose of stitching vias
which just connect one GND layer?
Once again, there are tens of thousands of designs shipping every day
with signals running at rates as high as 28 Gb/S (14 GHz) that do not have
stitching and perform very well. As I said before, most of these products
would be impossible to build if stitching was necessary for their proper
operation.
That fact that some do stitching does not demonstrate that it is
necessary nor do elaborate simulations. Once again unvalidated simulations
are worth the paper they are written on. We have way too many people doing
simulations and enforcing design constraints without first demonstrating
that the constraints are necessary.
That is simply not good engineering.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Shimko, Steve (ES)
Sent: Thursday, November 5, 2015 8:36 AM
To: istvan.novak@xxxxxxxxxxx; leeritchey@xxxxxxxxxxxxx;
dmarc-noreply@xxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Cc: bbakshan@xxxxxxxxx; Kevin.Hou@xxxxxxxxxx
Subject: [SI-LIST] Re: EXT :Re: What's the purpose of stitching vias
which just connect one GND layer?
Our RF group uses via stitching all the time. These are for 50 ohm RF
traces running on organic boards or ceramic substrates. These interfaces
are all single ended (think coax). Via stitching is also used to create
cavities where active components such as amplifiers are located. The vias
usually transverse several layers, picking up ground planes on the top and
bottom of the signal layer. They sometimes go all the way down through the
boards, though 20+ layers, when an RF signal has to routed from the top to
the bottom.
But, there also a large amount of simulation that is done when using vias
that way. Every trace, transition, and cavity is modeled using HFSS or CST
Microwave (or similar) suite of tools. With active devices that have gain
beyond 30 GHz, it is very easy to inadvertently create resonances that can
lead to oscillations and drop-outs.
Steve Shimko
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Istvan Novak
Sent: Wednesday, November 04, 2015 7:59 PM
To: leeritchey@xxxxxxxxxxxxx; dmarc-noreply@xxxxxxxxxxxxx;
si-list@xxxxxxxxxxxxx
Cc: bbakshan@xxxxxxxxx; Kevin.Hou@xxxxxxxxxx
Subject: EXT :[SI-LIST] Re: What's the purpose of stitching vias which
just connect one GND layer?
Lee,
As always, it depends. One of the presentations our team is going to do
at DesignCon 2016 will describe (with data) a scenario when stitching vias
are needed.
Regarding the original post though, if a stitching via is attached only
to one plane layer close to the surface (ground or power) it is prone to
quarter-wave resonance, which carries its own risks.
Regards,
Istvan Novak
Oracle
On 11/4/2015 7:51 PM, Lee Ritchey wrote:
Much speculation in this message! Where is the proof?and plane edges.
There are millions of PCBs shipped every month with who knows how many
very high speed transmission lines without stitching vias. In fact,
the products would be unroutable if stitching vias were required.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of heyfitch (Redacted
sender "heyfitch" for DMARC)
Sent: Wednesday, November 4, 2015 11:53 AM
To: si-list@xxxxxxxxxxxxx
Cc: leeritchey@xxxxxxxxxxxxx; bbakshan@xxxxxxxxx; Kevin.Hou@xxxxxxxxxx
Subject: [SI-LIST] Re: What's the purpose of stitching vias which just
connect one GND layer?
Had there been no stitching via, simulations would not have been
localized - just as the physical reality would not be localised. That
is both the simulation results would be sensitive to the BC
(proximity, type...), and the diff vias (e.g.) would couple thru
planes
Worse, simulations would not be predictive of the physical reality.
For CBCPW, you stitch to extinguish higher propagation modes, thus
preventing energy leaking into them from the diff and common modes.
Regards,
Vadim Heyfitch
Sent from my phone
On Nov 3, 2015, at 12:07, Boris Bakshan <bbakshan@xxxxxxxxx> wrote:
Best answer so far on the SI-list ! :) On Tue, Nov 3, 2015 at 9:51 PM,
Lee Ritchey <leeritchey@xxxxxxxxxxxxx>
wrote:
Those stitching vias keep the CAD department busy and raise the costCaveat and Virus Alert:
of the PCB. Not much else.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]
On
Behalf Of Kevin Hou
Sent: Monday, November 2, 2015 9:30 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] What's the purpose of stitching vias which just
connect one GND layer?
Hi Guru:
I found one interesting thing on Intel 6-layer(S-VCC-S-S-GND-S) CRB
about the stitching via.
There are pairs of stitching GND via put around the differential
signals(PCIe gen3) transited from TOP to BOTTOM layer.
The differential signal is VCC reference on the TOP layer and GND
reference on the BOTTOM layer.
My understanding for the stitching via is to provide the return path
(GND reference transited to another GND reference) But in the Intel
CRB I had on hand, these stitching vias are only connected to one GND
layer. What's the purpose?
Using capacitor to connect VCC/GND will be better, right?
Best Regards,
Kevin Hou
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