[SI-LIST] Re: EXT :Re: Ferrite Beads
- From: "Lee Ritchey" <leeritchey@xxxxxxxxxxxxx>
- To: <s.shimko@xxxxxxx>, <tgsmith81@xxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Mon, 7 Dec 2015 09:24:01 -0800
Now, that is a good SI answer>
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Shimko, Steve (ES)
Sent: Monday, December 7, 2015 4:29 AM
To: tgsmith81@xxxxxxxxx; si-list@xxxxxxxxxxxxx; leeritchey@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: EXT :Re: Ferrite Beads
We usually put a source termination resistor, 22 ohms to 33 ohms, at the
output of the clock oscillator, or even some other active device that may be
receiving the clock from an external source. This helps match the output
impedance of the oscillator or other device to the (nominally) 50 ohm signal
trace.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Tim Smith
Sent: Sunday, December 06, 2015 9:58 PM
To: si-list@xxxxxxxxxxxxx; leeritchey@xxxxxxxxxxxxx
Subject: EXT :[SI-LIST] Re: Ferrite Beads
On 12/6/2015 8:07 PM, Lee Ritchey wrote:
Why would one deliberately degrade a signal that way?
I have inherited this design; however I imagine that it was done in an
attempt to slow the edges of the clock signal in an effort to reduce the
higher frequency components.
I recall one of your seminars Lee where you recommend to keep edges slow.
If the clock signal is to be used by a PLL internal to the MCU, is not the
best signal to deliver a sine wave?
Whilst I appreciate the intention of the previous designer, I don't believe
using a potentially resonant circuit is the correct way to go about it.
On Mon, Dec 7, 2015 at 1:41 PM, Kevin G. Rhoads <krhoads@xxxxxxxxxxxxxx>
wrote:
On 12/6/2015 8:07 PM, Lee Ritchey wrote:
Why would one deliberately degrade a signal that way?
It was stated several posts back that it was intended to control the
edge rise time by that ...
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