[SI-LIST] Re: ESD is a low frequency event -really??
- From: Chris Cheng <Chris.Cheng@xxxxxxxxxxxx>
- To: "'MikonCons@xxxxxxx'" <MikonCons@xxxxxxx>, si-list@xxxxxxxxxxxxx
- Date: Thu, 18 Mar 2004 14:47:07 -0800
The way I see it, CY's control the absolute noise on the nodes and CX
control the fraction of the absolute noise that will appear as differential
noise across power and ground. You can either attack the fraction or the
absolute value to enhance your immunity.
Now let's see who gives a better bang for the buck.
Any sane designer has to start with some power/gnd pairs in a PCB (though
not BC). Without paying premiums for BC, you are looking at 3-4 mils
dielectric planes. If in a panic you switch to BC you can drop it to 1-2mil,
may be a little thinner if you pay an arm and a leg. So you are looking at a
1.5x-4x improvement in CX switching to BC.
Now if you completely leave the chassis open wrt logic ground, your CY will
probably be close to the plane capacitance between the PCB and the back side
of chassis a few mm away. That will be in ~pf/in^2.
However, if you provide a dead short with a bolt that tie the PCB logic
ground directly to chassis, you now parallel the bolt with that plane
impedance. At ~GHz the inductance of the bolt with a few mm in diammeter and
a few mm in length (across the PCB) will be in the ~nh range, and even
better if the frequency of interest decrease. So the dead short bolt will be
compatible if not better than the impedance of CY. Evertime you add a dead
short bolt, you drop the impedance by a proportional fraction. The good news
is, the bolt is almost free since chances are you have to mechanically tie
the PCB to the chassis anyways for shock and vibe reasons. It is just a
matter of isolating the tie point on PCB or shorting it to logic ground. So
if you need to drop CY by 2x-4x, short 2-4 bolts near your area of concern,
probably for free. And I believe that's what Doug's experiment shows.
Sometimes you get the "surprise" benefit from you disk or PC card vendors by
them shorting their logic ground to their chassis without even telling you.
Now that's the best bang for the buck.
-----Original Message-----
From: MikonCons@xxxxxxx [mailto:MikonCons@xxxxxxx]
Sent: Wednesday, March 17, 2004 4:47 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: ESD is a low frequency event -really??
Good comments and thoughts, guys. My thoughts follow.
**************
Steve's original model (with non-ideal capacitors):
vsource 1 0
R1 1 12
L1 12 13
CX 13 23
CY1 13 0
R2 1 22
L2 22 23
CY2 23 0
***************
This is a good model for dimensions where the lumped elements apply. Steve's
comments on a more complex (distributed) model would be necessary for the
higher frequency content of the leading edge of an ESD strike. The higher
frequencies are more likely to cause soft errors from the coupled
spikes/glitches. I
have used the essence of this model configuration in differential analog
signal
conditioning circuits to reduce CMV-induced errors since 1961, and it works
beautifully. The CMV rejection (i.e., the reduction in differential, or
normal-mode, voltage conversion from injection of common-mode voltage) is
inversely
related to the relative size of Cx to Cy. This means one can have a total
imbalance in Cy1 versus Cy2 and compensate for it by a large ratio of Cx to
Cy. The
impact of differences between R1 and R2 is also beneficially reduced.
You can model it or do the math, but the result is the same. Where Cx (in
our
case, the BC value) is substantially larger than Cy (i.e., the coupling from
either the ground or power plane to chassis in the model(s) noted), then any
voltage coupled to the circuit is forced to be primarily CMV. When BC is
used,
a representative ratio of Cx to Cy for a small 25 square inch PCB is ~2500:1
or ~68 dB. If the coupling from chassis to the power and ground planes is
the
same within 10% (i.e., Cy1 and Cy2 are within 10% of each other in value),
an
additional 20 dB of rejection is added. A larger PCB gets proportionally
better rejection (e.g., a 10 x 10 inch PCB would demonstrate a further 12 dB
improvement).
*********
Now, given that one uses the (now infamous) chassis ground rings that I
recommend for some applications, the imbalance in Cy1 and Cy2 can easily be
held to
5% or less, which adds another 6 dB of improvement. In summary, a 100 square
inch PCB designed with two BC sandwiches (which yields ~1 nF/square inch)
and
chassis ground rings can be expected to exhibit ~106 dB rejection of an
ESD-induced voltage (or from any other external source of EMI).
*********
To address the numbers requested by Steve, one has to estimate the values of
Cy1 and Cy2, identify the PCB size, and calculate the expected CMV rejection
(i.e., conversion to normal-mode voltage). I haven't provided specific
numbers
before as there are clearly some caveats and special conditions that apply
to
each unique design. Additionally, be aware that any modeling and associated
analysis will be altered by the frequency range over which the prediction
will
apply. Assuming ESD is the source of concern, the lowest frequency content
of
the strike will be beneficially affected by the bulk capacitors (as well as
the
many typical ceramic capacitors) of the PDS design. The midrange frequencies
(up to ~50 MHz) will benefit from the ceramic capacitors. Beyond ~50 MHz and
up into the GHz region (where most soft errors are induced in today's
designs),
the BC capacitance will be most effective. **************
Note that many designs that are not directly exposed to the high frequency
content of the leading edge of an ESD strike (as typically applies in a
shielded
enclosure) are reasonably protected by a good PDS design that DOES NOT HAVE
TO HAVE BC content. This is most likely the reason that Chris Cheng has
demonstrated success without the use of BC techniques. The shielding effect
of a
conducting enclosure improves with increasing frequency because of the
lesser
depth penetration due to the frequency dependence of skin effect.
***********
Hopefully, the above comments will explain why one can't simply give a
simple
guideline or a couple of formulas for prevention or correction of ESD (or
other radiated susceptibility) problems.
Respectfully,
Mike
Michael L. Conn
Owner/Principal Consultant
Mikon Consulting
Cell: 408-821-9843
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