I used to believe power noise is important to channel analysis in the following
respect :
a) power noise on clock sources (in particular in PLL based clock synthesizers)
will generate jitter accumulation which we will rely on PHY dependent jitter
transfer curves to eliminate (or tracked) by Tx and Rx circuits. The remaining
part will be mistakenly (together with crosstalk in channels) considered as BUJ
or even Rj if your jitter decomposition method is not robust.
b) another area of confusion is substrate or on die supply noise that get
accumulated through the Rx PLL and appears as timing uncertainty at the slicer
sampling point in time.
I will consider a) as a jitter transfer problem and b) as jitter accumulation
problem.
If you buy what I said above, you can have the best power models in the world,
you will still have a hard time figuring out what is the excitation to that
"power system" and how to couple those noise into a ultra-complicated SerDes
that you can't even model properly without considering the power noise.
With advances in CDR and Tx sourcing circuits, we are looking at jitter models
that cannot even be described by traditional PLL loop dynamics (bang-bang phase
detectors, LC tank VCO). Now I don't even know how to describe b) any more.
Chris Cheng
Distinguished Technologist , Electrical
Hewlett-Packard Company
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Ramesh Ponnada
Sent: Wednesday, September 02, 2015 11:04 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Do SERDES interfaces need Power Aware SI channel simulation
*Hi Team,*
Could anybody let me know the importance of Power Aware simulation in today
High Speed applications.
I saw lot of example on Power Aware SI simulation for Parallel interfaces like
DDR3/4. Since, its parallel bus protocol, issues like SSN, ground bounce,
Impedance profile should be maintained.
But for SERDES interfaces like USB 3.1, PCIe 3.0, HDMI..etc do we need to
consider Power Aware channel and Chip simulation...? What kind of PDN issues
do SERDES interfaces causes...?
I believe that since SERDES are Differential signalling and they are
independent of Power effects on PCB board...Please correct me if i am wrong.
Thanks in advance....
Regards,
*Ramesh*
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