[SI-LIST] Re: Distribution/Filtering/Decoupling Guide The 100Mhz clean cutt off.

  • From: Chris Cheng <Chris.Cheng@xxxxxxxxxxxx>
  • To: "'Charles Grasso'" <cgrassosprint1@xxxxxxxxxxxxx>,Chris Cheng <Chris.Cheng@xxxxxxxxxxxx>,"'Larry Smith'" <Larry.Smith@xxxxxxx>
  • Date: Thu, 15 Jan 2004 18:56:40 -0800

Well, I will give it a try based on what I now see as a complete picture of
what's going on with Larry's example.

Disclaimer first
Since I was responsible for a lot of packaging and module designs in Larry's
company before I departed many years ago, I have to say I have never seen or
reviewed or involved in any of the current or whatever future generation
package or module he is referring to. Everything I am saying is simply based
on what Larry has disclosed in this public forum. If my guess is wrong,
please accept my apology.

To begin the discussion, I have to requote Zhiping's question below on how
to "shift the power integrity problem to the PCB level". I claim there is a
hard limit of 100MHz on the package power distribution, by that I mean with
the existing number of pins/sockets and package caps and on die decoupling,
all the available decoupling charge on the package and die will be consumed
and core voltage will start to drop after 10ns of continues current drain on
die. Something on the PCB and external DC/DC regulator has to start
providing the charge to maintain the voltage level on die. By the same
token, due to the exiting impedance at the pins/socket and package, the
system (PCB or regulator) cannot reach the Si core power faster than 100MHz.
This is based on an optimized pin analysis where I want to provide the least
amount of power and ground pins (if you ship a huge volume, like a 100M of
them, @ a few cents per pin, you save a LOT of money) that can maintain the
minimum core noise level on die. The added benefit of it is you don't need
to demand exotic >100MHz decoupling outside the package (since it won't help
anyways) and you also don't need to over kill your decoupling on package by
providing <100MHz decoupling bulk caps, just pass that responsibility to the
system folks.

Now let's say you throw in too many power and ground pins on your package.
Not only does it cost you money (@ a few cents per pin), it now also starts
to perforated your PCB power and gnd planes to the extend that the PCB to
package impedance starts to pick up (shifting below 100MHz). Now you really
need to have a thin core PCB to lower the impedance back to equal the case
when you have less power/ground pins with a smaller package. But in a sense,
this is exactly what Zhiping was asking for, shifting some of the integrity
problem to the PCB level. You can over design to an extend that what happen
in the PCB really start to impact the package performance. 

It's your choice, too many pins and you will need BC and cost you $$$$$$,
just enough pins and you don't need BC and save you some $ also. But if you
don't have enough pins, you are dead and no system or PCB design can save
you.

As a side note for those who want to built benchmark system design to
evaluate system to package distribution, good luck ! If you think you can
pick up something as subtle as the above, my hats off to you. I have enough
trouble doing a unique case where I know everything ahead of time.

Same old song here, there is no need for BC. Hey, that may be in my second
broken record.

-----Original Message-----
From: Charles Grasso [mailto:cgrassosprint1@xxxxxxxxxxxxx]
Sent: Thursday, January 15, 2004 5:34 PM
To: Chris.Cheng@xxxxxxxxxxxx; 'Larry Smith'
Cc: scott@xxxxxxxxxxxxx; silist
Subject: Distribution/Filtering/Decoupling Guide The 100Mhz clean cutt
off.


Chris, Larry et al...

Can you please explain the 100MHz clean cut so often mentioned in ths
thread? Is it bandwidth (i.e related to rise time?) is it the crystal or...

Puzzled.
Chas in Colorado..


-----Original Message-----
From: zhiping yang [mailto:zhiping@xxxxxxxxx]
Sent: Tuesday, January 13, 2004 5:55 PM
To: Chris.Cheng@xxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] Re: Power Supply
Distribution/Filtering/Decoupling Guide]


Hi Chris,

Thank you for sharing your thoughts and Very good points about the power
integrity.

One comment about your "total system approach".  Technically speaking, it is
best to put the equal amount of efforts on the die, package and PCB power
distribution since they are equally important in the complete power delivery
system.  More important, the PCB COULD NOT fix the problems with the die and
package power delivery systems in some cases.

In the real word, when cost and $$ is involved, the trade-offes must be
made, so the design may not be optimized in technical side.  For example,
due to the high cost of die size increase and package limitations, it may be
more cost effective by shifting the power integrity problem to the PCB level
at a certain degree.  This may require using BC or more decoupling caps on
the board, but it could still be cost effective from the "total system"
point view.

This is my $0.02 input.  Thanks.

Zhiping
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field

or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list

For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field

List technical documents are available at:
                http://www.si-list.org

List archives are viewable at:     
                //www.freelists.org/archives/si-list
or at our remote archives:
                http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
                http://www.qsl.net/wb6tpu
  

Other related posts: