[SI-LIST] Re: Disscussion on DRAM technoly
- From: Tesla <emcesd@xxxxxxx>
- To: hermann.ruckerbauer@xxxxxxxxxxxxx
- Date: Wed, 13 Jun 2012 16:45:56 +0800 (CST)
Hi, Hermann
You really are a expert of DRAM.
I may need some time to digest it.
Best Regards.
Tesla.
At 2012-06-13 16:36:20,"Hermann Ruckerbauer"
<hermann.ruckerbauer@xxxxxxxxxxxxx> wrote:
>Hello,
>
>there have been done several attempts to standardize a serial IO on
>Memory. There are several isues:
>
>1)
>- The DRAM process is optimized to provide low leakage in the Array. It
>is not simple to generate any high speed logic based on theis process
>(thats one o fthe reasons why we see VDD termination on DRAMs )
>- Serialization costs time and high speed data transmission requires as
>framed protocoll with Error correction
>- Going to a unidirectional interface might not save that much pin and
>would change the protocoll and need to be adjusted to DRAM internal
>functionallity .. so it is not just to connect an PCIe interface to a
>DRAM device
>- Maybe even the bigger issue: Customer know the parallel architecture
>since years ...
>- the high speed circuits need to be implemented on each DRAM. Currenly
>the power consuming high speed stuff is on the controller only. Adding
>CDR's on each DRAMs would kill the power budget of a DIMM quite fast
>- When adding e. g. an PLL it is much more difficult to set a DRAM in
>PowerDwon and wake it up fast
>- ...
>
>so overall usually these attempts have been killed by Power, latency,
>customer acceptance ...
>
>2)
>- Graphics do have On Die Termination on the CA. On DIMM level this is
>not efficiant, as it would be built into all devices, but only used on
>one (the last on the fly by bus). As in the standardization commites
>there are mainly people active that use DIMM based application they did
>not want to put the cost on 8 DRAMs (not sure if this is a real cost
>saving). A distributed Termination on all DRAMs does not work very
>well. Additionally one would need additional methods to identify the
>DRAM to Terminate wich requires Protokoll (MRS) changes or an additional
>Ball (that is not easy available).
>- If termination would be enabled on all devices all devices would burn
>more Power. If it just enabled on the last one this a a complete
>different power budget. Most likely this would be a similar thevenin
>Termination as on the DQs. This are 25 more signals taking some current
>over the Termination.
>
>==> this one was checked several times, but was never implemented in
>commodity, as in there has not been enough interst from the industry in
>JEDEC ...
>
>theres are much more Points on both topics, but this is just a short
>overview ...
>
>Hermann
>
>
>
>
>Our next Events:
>================
>
>"Open the Black Box of Memory"
>Seminar on 09/10. October 2012
>
>Check our website or contact us for details
>
>EKH - EyeKnowHow
>Hermann Ruckerbauer
>www.EyeKnowHow.de
>Hermann.Ruckerbauer@xxxxxxxxxxxxx
>Veilchenstrasse 1
>94554 Moos
>Tel.: +49 (0)9938 / 902 083
>Mobile: +49 (0)176 / 787 787 77
>Fax: +49 (0)3212 / 121 9008
>
>
>schrieb Tesla:
>> 1Why not use Serdes as I/O interface?
>>
>> Serdes I/O technology became faster and faster now has may advantage compare
>> with parrelel bus, why not use Serdes for memory interface such as DDR(Next)?
>>
>> 2Why not use ODT for CMD/CTL/ADD signal lines?
>>
>> Use ODT for CMD/CTL/ADD signal lines, this will save us a lot time and
>> money. why not make the termination in chip?
>>
>> Thanks.
>>
>> Tesla
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