[SI-LIST] Re: Differential via optimization
- From: "Antonis Orphanou" <orphanou@xxxxxxxxxxxx>
- To: "emcesd@xxxxxxx" <emcesd@xxxxxxx>, "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Tue, 16 Oct 2012 18:46:12 +0000
Hello Tesla,
In optimizing a via both Z11 and Z12 are parameters you need to consider;
their values are inter-related and are a function of your optimizing parameters.
If Z12 is high then you need a lot of clearance on the antipad. Parameters like
the distance between p&n, their respective distance to the ground and the
anti-pad size are variables than can optimize a line. Fix two and vary the
third and you will get a different solution for the via geometry.
Thx
Antonis.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Tesla
Sent: Tuesday, October 16, 2012 2:01 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Differential via optimization
Hi,
I optimizated a differential via on PCB using 3d EM software. The main goal is
to make SDD11 as small as possible. i use antipad radius size of 15,25 and
30mils respectively. I found the 30mils antipad size give the best SDD11
results.
The doubt now is that i never see high speed board use the such large antipad
size(Like Altera or Xilinx's Demo kit). Are there some PCB fab issues or Maybe
I got something wrong?
Thanks anb Best Regards.
Tesla.
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