[SI-LIST] Re: Differential via optimization
- From: Istvan Novak <istvan.novak@xxxxxxxxxxx>
- To: emcesd@xxxxxxx
- Date: Tue, 16 Oct 2012 07:47:34 -0400
Tesla,
Beyond a certain point increasing antipad size can cause multiple issues.
As Siddharth said, it can cause power related issues. In high-power chips
in the BGA pinfield the perforation raises DC resistance, which can create
too much voltage drop. If this is a point-of-load application for the DC-DC
converter and it has remote sense pins (both high and low sides), you
can compensate for the extra DC drop. With multiple loads on the same
DC-DC converter, however, this always has limited success. The plane
perforation raises the power-ground plane pair impedance locally in the
pin field, creating new plane resonances. And equally importantly it
becomes
a signal-integrity issue, when the large antipads leave very little webbing
for the traces to serve as return current path. In larger pinfields with
regular pin pitch, such as under large packages and connectors, the
periodic nature of disturbance on the traces not only increases the
average impedance of the traces, but also creates sharp resonance
suckouts in the transfer functions. You can find details about these
effects in the papers our team did a few years back, among others:
- DesignCon 2012, Santa Clara, CA, January 30 - February 2, 2012
"Vias, Structural Details and their Effect on System Performance"
- DesignCon2011, Santa Clara, CA, January 31 - February 3, 2011
"Examining the Impact of Power Structures on EM Model Accuracy"
- DesignCon2008, Santa Clara, CA, February 4-7, 2008
"Impact of PCB Laminate Parameters on Suppressing Modal Resonances"
- DesignCon2007, Santa Clara, CA, January 29-31, 2007
"Crosstalk due to Periodic Plane Cutouts"
You can get them from http://www.electrical-integrity.com/
Regards,
Istvan Novak
Oracle
On 10/16/2012 5:00 AM, Tesla wrote:
> Hi,
>
> I optimizated a differential via on PCB using 3d EM software. The main goal
> is to make SDD11 as small as possible. i use antipad radius size of 15,25 and
> 30mils respectively. I found the 30mils antipad size give the best SDD11
> results.
> The doubt now is that i never see high speed board use the such large antipad
> size(Like Altera or Xilinx's Demo kit). Are there some PCB fab issues or
> Maybe I got something wrong?
>
> Thanks anb Best Regards.
>
> Tesla.
>
>
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