Vincenzo, Unfortunately the best case scenario is running USB diff tracks a = distance of about 200mm. If I could do I would reduce the lengths.=20 I want to avoid the high speed USB kit as I am running the USB kit in an = environment with some sensitive radio equipment. I dont want to jam my = radio kit! Any idea on the track dimensions etc ? =20 Steve Rogers B.Eng (Hons) C.Eng IEE RF Design Engineer Micromill Electronics Limited Leydene House Waterberry Drive=20 Waterlooville Hampshire PO7 7XX Tel: +44 (0) 23 9236 6600 Fax: +44 (0) 23 9236 6673 Registered No. 1456922 (England). =20 Registered Office Brook Road Wimborne, Dorset BH21 2BJ *********************************************************************** "This email and any attached files are confidential and may be legally = privileged.If you are not the addressee, any disclosure, = reproduction,copying, distribution,, or other dissemination or use of = this communication is strictly prohibited. If you have received this = transmission in error please notify the sender immediately and then = delete this email. It is the policy of Micromill Electronics Limited that no legally = binding statements, representations or commitments (collectively = 'statements') may be made by email. Any such statements must be = confirmed either by facsimilie or by post before they will have legal = effect. The sender of this email is not authorised to commit the company = in any way and the addressee is hereby formally notified of that fact." *********************************************************************** -----Original Message----- From: Vincenzo Kreft-Kerekes [mailto:vincenzo@xxxxxxxxxxxxxx] Sent: Thursday, January 22, 2004 4:07 PM To: Steve Rogers Cc: si-list@xxxxxxxxxxxxx Subject: Re: Differential trace Characteristic Impedance Steve, Quick question diverging from differential trace impedance: What = distance do these USB traces need to cover? Does running them "around the board" = mean literally around a bunch of components. What's the geometry here? Do you have the board space to place a PHY or other receiving device direcly = next to the connector and worry about getting an 8 bit bus at some 20 Mhz = around the board instead of dealing with differential impendances at 480Mhz? Apple's new server modules for instance have I believe two Firewire 800 (1Gb/s, .5ns edge) ports spaced far apart and one PHY on each port to = avoid routing the differential traces for long distances. Also, when I see USB 1.1 mentioned, are you sure you don't want to use a high-speed PHY with USB 2.0 instead? They come in much smaller packages = than USB 1.1 PHYs and your product would be as fast as USB can be for some = time to come. Best, Vincenzo -----Original Message----- From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Steve Rogers Sent: Thursday, January 22, 2004 5:55 AM To: Doug Brooks; Fred Balistreri; steve weir; mediwheel_js Cc: si-list@xxxxxxxxxxxxx Subject: [SI-LIST] Re: Differential trace Characteristic Impedance First thanks for your help guys. Taking all you have said into consideration it seems like I either need = =3D to use a field solver, the Ultra-cad program or guess! While I decide on the way to go consider the following:- 1. I could space my tracks far enough so that I could use the simple =3D equations from national semiconductor. This is great but how far apart = =3D do the tracks need to be in order that they have no affect on each =3D other. Next, I would think that this approach is wasteful of board =3D surface area given all the unused space between the diff tracks. This = =3D said there are probably some benefits of doing things this way. Theres = =3D bound to be somthing good about having a very small contribution of diff = =3D Zo made up from coupling between tracks? 2. Going the other way I can try to claw back the lost space between the = =3D tracks. Once I do this the diff Zo begins to drop from twice the =3D isolated single track Zo value. In order to compensate I then just need = =3D to reduce the thickness of the tracks. This is nice as within sensible = =3D limits I end up with an even more narrow overall structure =3D (trace-space-trace). Of course The board house must be able to manufacture the trace and gap. = =3D With this approach We have the opposite situation with a large =3D contribution of diff Zo coming from fringe field or coupling between =3D traces (whatever you want to call it). Is this a clever thing to do? I = =3D would imagine that the tolerance with this approach is going to be a lot = =3D worse. Any comments? =3D20 Steve Rogers B.Eng (Hons) C.Eng IEE RF Design Engineer Micromill Electronics Limited Leydene House Waterberry Drive=3D20 Waterlooville Hampshire PO7 7XX Tel: +44 (0) 23 9236 6600 Fax: +44 (0) 23 9236 6673 Registered No. 1456922 (England). =3D20 Registered Office Brook Road Wimborne, Dorset BH21 2BJ ________________________________________________________________________ This email has been scanned for all viruses by the MessageLabs Email Security System. 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