[SI-LIST] Re: Diff.Pairs

  • From: esayre <esayre@xxxxxxxx>
  • To: chris.cheng@xxxxxxxxxxxx, "'mchin@xxxxxxxxx'" <mchin@xxxxxxxxx>,"'si-list@xxxxxxxxxxxxx'" <si-list@xxxxxxxxxxxxx>
  • Date: Mon, 13 Oct 2003 23:12:26 -0400

Dear fellow colleagues:

It should be clear from the many interchanges on this subject that there 
are lots of ways to design differential pairs ranging from uncoupled to 
coupled using either edge coupled or broadside or uncoupled traces on 
different layers. The design style used should be a manifestation of 
thoughtful engineering decisions relating to the specific design underway. 
All the methods are valid implementations or differential transmission 
systems each with well defined design paradigms and parameter sensitivities.

It is important to remember that the first design rule in logic card work 
is get the whole design to fit and this sometimes makes us favor one 
approach over another especially if it worked the last time! There is no 
magic or "witch-craft" (Halloween Season joke!) to differential 
interconnects.  All mentioned implementations work when designed properly, 
although there is evidence that edge coupled lines will, at some data rate, 
have larger losses due to "edge crowding and knife edge exponential loss 
effects". These edge effects reduce the effective high frequency conduction 
area resulting in slightly higher skin losses than the equivalent broadside 
coupled design.  It's all about symmetry and current distribution.

Broadside coupling is not very sensitive to horizontal mis-alignment until 
the mis-alignment is on the order of a trace width.  The fields do not mind 
bending.  Edge coupled line impedances are sensitive to the material that 
is removed between coupled traces, so this implementation is sensitive to 
the accuracy of the etch process and trace copper weight.  When traces are 
completely uncoupled, as they seem be in one of Lee Richey's designs, there 
is no coupling sensitivity  but the traces must be identical in impedance 
or they will exhibit differential mode to common mode energy conversion due 
to impedance asymmetry.  To be right on the money, confirming calculations 
must be made with the actual PCB dielectric constants (Dk's) and finished 
thicknesses of the dielectric materials.

All differential PCB trace designs are prone to impedance errors  when the 
trace width gets down to the 4mil width range since that's getting down to 
edge placement  accuracy or alignment accuracy limits.  When the copper is 
deposited onto the PCB (so called additive processes)  to form the traces, 
the accuracy is much better so that the impedance comes closer to design 
parameters but the process is more expensive.  The lesson here is don't use 
4mil lines if you can help it, especially when they form a coupled 
differential pair for any appreciable distance.

Lastly, concerning the effect of plane breaks, differential mode currents 
are not affected by the break because they cancel, and the plane acts as a 
virtual equipotential surface or plane.  However, if there is a common mode 
current component present in the PCB trace currents due to skew or driver 
unbalance, the plane break will radiate since the break looks like a 
magnetic dipole or slot antenna fed by common mode currents.  The resultant 
radiated field strength is related to the resonant antenna properties of 
the slot and the applied fundamental signal frequency.  If the fundamental 
frequency and antenna radiating resonance are close, the slot or break will 
radiate strongly. ( See any book on antennas for more detail.)


ed sayre
At 11:52 AM 10/13/2003 -0700, Chris Cheng wrote:
>What you are suggesting below is "tight coupling" of differential pair. Lee
>was bragging about not needing any coupling for differential pairs. If what
>he claims and what you mentioned below is the same, he will be contradicting
>I am still waiting for him to answer my question :
>"I would like you to answer a simple question :
>If tomorrow you are going into a client's office to consult on designing a
>2.4GB/s differential signal system. Will you recommend them to "routed
>thousands of differential signal where each member of the pair is on a
>different layer". Do you think that is good engineering practice ? Do you
>think you can still keep your job as a consultant after making that
>statement ?"
>Like the famous quote, "I will be waiting until hell freeze over".
>-----Original Message-----
>From: Michael Chin [mailto:mchin@xxxxxxxxx]
>Sent: Sunday, October 12, 2003 10:40 AM
>To: scott@xxxxxxxxxxxxx
>Cc: bmgman@xxxxxxxxxx; si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Re: Diff.Pairs
>I've followed your emails exchanges with Mike Brown
>closely.  This subject is a very important item as we
>tackle high speed design using differential pairs.
>Today, we have differential pair in CMOS logic,
>LVDS, and differential HSTL (RLDRAM).
>Both of you have argued with very good points and I
>appreciated your thoughts.  But in this case, I would
>side with what Lee has stated.  He may not have explicitly
>stated the stackup in his assumption, but it is commonly
>referred as the the broad side coupled differential pair
>vs. edge coupled stripline differential pair.
>There is no question about the benefits and level of
>control from edge coupled differential where both tracks
>are routed on the same layer.  But it is also very common
>to have a dual stripline layers between two Ground layers
>for broadside coupling.  This is mostly used in the backplane
>side and have demonstrated success in many designs.
>An example of this stackup can be:
>=============   Ground plane for image return
>                  Core, thickness H
>      =====       Diff Layer #1
>                  Prepreg
>      =====       Diff Layer #2
>                  Core, thickness H
>=============   Ground plane for image return
>I have been to a lot of seminar where SI experts argued
>the Pro/Con of edge coupled vs. broadside coupled differential
>pair. I have seen good results from both styles on frequency
>under 3GHz.
>Just my two cents,
>Michael Chin
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